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review document - seagate - d a t a b o o k version 1.0 september, 2003 INIC-1622 pci to serial ata host adapter ic
confidential INIC-1622 data sheet revision notes for INIC-1622 data book: p/n 1622x-ds rev 1.0, 9/24/03 revision history doc rev 1.0 (p/n 1622x-ds) 09/24/03 (current release) technical information changes in this data book release the table below lists technical information that has changed from the INIC-1622 data book revision x.0 to the INIC-1622 data book revision 1.0 . all changes are identified in the manual by change bars in the left-hand column (superficial or non-technical edits are not indicated). section updated pages affected change description all all initial release. INIC-1622 data sheet confidential
INIC-1622 features copyright copyright? 2003 initio corporation. all rights reserved. no part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any, electronic, mechanical, photocopying, recording without the express written consent and authorization of initio corporation, 650 north mary ave., sunnyvale, ca 94085 trademarks initio, inic-, are registered trademarks of initio corporation. change initio corporation reserves the right to make changes in the product design without reservation and without notification to its users. the material in this publication is for information only and is subject to change without notice. pci 32 bit/66 mhz interface ? pci 2.3 compliant interface. ? burst transfer rate of 264 mb/s. ? built in hardware bus master engine. ata interface ? serial ata revision1.0. ? serial ata transfer rate of 1.5 gb/s. ? supports two sata channels. memory interface ? support for 512k flash and serial e 2 prom. data fifo ? 256 byte data fifo for each channel. on board pci bus master engine ? on board bus master engine relieve the system processor from book keeping and enhance perfor- mance. uses initio?s proprietary host adapter mode of operation ? initio proprietary autodma mode (idma) ? queued/overlapping ata commands support other features ? disk raid 0/1 support. ? sata hot plug/unplug hardware support. ? implements power management ? full driver support for all major operating systems. ? bios supports dos and windows applications without driver involvement. ? supports plug and play allowing users to change configurations without the use of jumpers. INIC-1622 data sheet confidential
INIC-1622 data sheet confidential i table of contents section 1 - overview ................................................................................................................................ .............. 1 1.1 introduction ................................................................................................................................ .................. 1 1.1.1 feature summary .............................................................................................................................. 1 1.1.2 reference documents ....................................................................................................................... 2 section 2 - pin definitions ................................................................................................................................ ..... 3 2.1 pci interface pins ................................................................................................................................ ....... 4 2.1.1 non supported pci-32 pin signals ................................................................................................... 4 2.2 memory interface pins ................................................................................................................................ . 5 2.3 sata interface pins ................................................................................................................................ .... 5 2.4 hardware configuration pins ...................................................................................................................... 6 2.5 power and ground pins ............................................................................................................................... 6 section 3 - address mapping summary .............................................................................................................. 7 3.1 configuration spaces address map ............................................................................................................ 7 3.2 ata shadow registers ............................................................................................................................... 8 3.2.1 command-block register ................................................................................................................. 8 3.2.2 control-block register ..................................................................................................................... 8 3.2.3 register for the packet and service commands ...................................................................... 8 3.3 i/o & memory mapped registers address map ......................................................................................... 9 3.3.1 page 0 registers ................................................................................................................................ 9 3.3.2 page 1 registers .............................................................................................................................. 10 3.4 command parameter blocks (cpb) structure definition ......................................................................... 11 3.5 physical region descriptor ( prd ) structure definition ........................................................................... 11 3.6 summary of supported pci commands .................................................................................................... 11 section 4 - register descriptions ........................................................................................................................ 13 4.1 configuration space register descriptions ............................................................................................... 13 4.2 page 0 i/o & memory mapped register descriptions .............................................................................. 29 4.3 page 1 i/o & memory mapped register descriptions .............................................................................. 53 4.4 idma sspll i/o register descriptions .................................................................................................. 58 4.5 command parameter blocks (cpb) register descriptions ....................................................................... 60 4.6 prd structure register descriptions ........................................................................................................ 65 INIC-1622 data sheet confidential
ii confidential INIC-1622 data sheet table of contents section 5 - electrical specifications ................................................................................................................... 67 5.1 absolute maximum ratings ...................................................................................................................... 67 5.2 recommended operating conditions ....................................................................................................... 67 5.3 general dc characteristics ....................................................................................................................... 68 5.4 pci dc parameters ................................................................................................................................ ... 69 5.5 pci ac parameters ................................................................................................................................ ... 70 section 6 - timing specifications ....................................................................................................................... 71 6.1 general timing ................................................................................................................................ ......... 71 6.1.1 ac input/output timing parameters ............................................................................................. 71 6.1.2 clock timing parameters ............................................................................................................... 72 6.1.3 clock skew timing parameters ..................................................................................................... 72 6.2 pci bus timing ................................................................................................................................ ......... 73 section 7 - packaging specifications ................................................................................................................. 75 7.1 INIC-1622 tqfp packaging specifications ............................................................................................. 75
INIC-1622 data sheet confidential 1 section 1 overview 1.1 introduction the INIC-1622 provides advanced host adapter features in a single 128 pin tq fp package with 2 serial ata and a 32 bit/66 mhz pci 2.3 compliant interface. the third memory interface allows access to flash and serial e 2 prom devices. the flash interface provides read/write access to the attached bios. the serial e 2 prom interface provides read/write access to the attached serial e 2 prom for bus configuration information. 1.1.1 feature summary pci 32 bit/66 mhz interface ? pci 2.3 compliant interface. ? burst transfer rate of 264 mb/s. ? built in hardware bus master engine. ata interface ? serial ata revision1.0. ? serial ata transfer rate of 1.5 gb/s. ? supports two sata channels. memory interface ? support for 512k flash and serial e 2 prom. data fifo ? 256 byte data fifo for each channel. on board pci bus master engine ? on board bus master engine relieve the system processor from book keeping and enhance performance. uses initio?s proprietary host adapter mode of operation ? initio proprietary autodma mode (idma) ? queued/overlapping ata commands support other features ? disk raid 0/1 support. ? sata hot plug/unplug hardware support. ? implements power management ? full driver support for all major operating systems. ? bios supports dos and windows applications without driver involvement. ? supports plug and play allowing users to change configurations without the use of jumpers. INIC-1622 data sheet
2 confidential INIC-1622 data sheet overview section 1 figure 1-1 INIC-1622 block diagram 1.1.2 reference documents ? peripheral component interconnect (pci) local bus interface specification, rev. 2.3 ? serial ata specification, revision 1.0 ? serial ata ii: extension to serial ata 1.0 rev. 1.0 pci slave registers data fifo 0 ch0 transport serial eprom flash 32 bit/66 mhz pci interface serial ata 0 1.5 gb/s local bus interface serial e 2 prom and flash logic ch0 pci master & prd engine serial ata 1 1.5 gb/s ch0 phy ch0 link pci bus arbitor data fifo 1 ch1 transpo rt ch1 pci master & prd engine ch1 phy ch1 link serial eprom
INIC-1622 data sheet confidential 3 section 2 pin definitions figure 2-1 shows the pinout of the inic- 1622 . figure 2-1 INIC-1622 tqfp pin assignments 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 m a 2 m w r n m r d n m a 3 m a 4 m a 5 m a 6 v d d i o v s s m a 7 m a 8 m a 9 m a 1 0 m a 1 1 v d d c v s s m a 1 2 m a 1 3 l e d 0 m a 1 4 m a 1 5 m a 1 6 m a 1 7 m a 1 8 t e s t m d 0 m d 1 m d 2 m d 3 m d 4 m d 5 m d 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pad0 nvrsd nvrck vdda rxp1 rxn1 gnda vdda gnda txn1 txp1 gnda vdda rxp0 rxn0 gnda vdda gnda txn0 txp0 gnda vddp vddp extr gnda clki/xtali xtalo vddio scan_en mcsn ma0 ma1 INIC-1622 128-pin tqfp top view 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 pcbe2n pad16 pad17 pad18 vss vddio pad19 pad20 pad21 pad22 pad23 pidsel pcbe3n pad24 pad25 vss vddc pad26 pad27 pad28 vss vddio pad29 pad30 pad31 preqn pgntn pclk prstn pintan led1 md7 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 p a d 1 p a d 2 p a d 3 p a d 4 p a d 5 v s s v d d i o p a d 6 p a d 7 p c b e 0 n p a d 8 p a d 9 p m 6 6 e n p a d 1 0 p a d 1 1 v s s v d d c p a d 1 2 p a d 1 3 p a d 1 4 p a d 1 5 v s s v d d i p c b e 1 n p p a r p s e r r n p t r d y n p d e v s e l n p s t o p n p e r r n p i r d y n p f r a m e n confidential
4 confidential INIC-1622 data sheet pin definitions section 2 2.1 pci interface pins 2.1.1 non supported pci-32 pin signals irqb# tck irqc# tdi irqd# tdo lock# tms sbo# trst# sdone# table 2-1 pci interface pins symbol tqfp pin # type description pad[31:00] 72-74,77-79,82-83,86-90, 93-95,108-111,114-115, 117-118,120-121,124-128,1 i/o, t/s pci address and data bus pcben[3:0] 84,96,105,119 i/o, t/s bus command and byte enables ppar 104 i/o, t/s even parity pframen 97 i/o, s/t/s cycle frame ptrdyn 102 i/o, s/t/s target ready pirdyn 98 i/o, s/t/s initiator ready pidsel 85 i initialization device select pdevseln 101 i/o, s/t/s device select pstopn 100 i/o, s/t/s stop current transaction preqn 71 o bus request pgntn 70 i bus grant pintan 67 o/d interrupt a perrn 99 i/o, s/t/s parity error pserrn 103 o/d system error pclk 69 i pci clock prstn 68 i pci reset pm66en 116 i pci 66 mhz enable
section 2 pin definitions INIC-1622 data sheet confidential 5 2.2 memory interface pins 2.3 sata interface pins table 2-2 memory interface pins symbol tqfp pin # type description ma[18:0] 56-52,50,49,46-42,39-36, 33-31 i/o memory address bus md[7:0] 65-58 i/o, t/s memory data bus mwrn 34 o memory write strobe mrdn 35 o memory read strobe mcsn 30 o bios flash/eprom chip select nvrck 3 o nvram serial clock nvrsd 2 i/o nvram serial data test 57 i test control table 2-3 sata interface pins symbol tqfp pin # type description tx p0 20 o channel 0 differential transmit positive signal line tx n0 19 o channel 0 differential transmit negative signal line rx p0 14 i channel 0 differential receive negative signal line rx n0 15 i channel 0 differential receive negative signal line tx p1 11 o channel 1 differential transmit positive signal line tx n1 10 o channel 1 differential transmit negative signal line rx p1 5 i channel 1 differential receive negative signal line rx n1 6 i channel 1 differential receive negative signal line clki/xtali 26 i external clock input or crystal oscillator output xtalo 27 o crystal oscillator output extr 24 i external reference resister led0 51 o channel 0 activity led led1 66 o channel 1 activity led
6 confidential INIC-1622 data sheet pin definitions section 2 2.4 hardware configuration pins the following signal pins are used during system reset (prstn) to select system specific function modes. 2.5 power and ground pins table 2-4 hardware configuration pins symbol tqfp pin # description function md 0 68 reserved reserved md 1 69 reserved reserved md 2 70 nvram load default pulldown = load vendor specific configuration space values pullup = configuration space uses on chip default value md 3 71 fast back-to-back enable pulldown = fast back-to-back disable pullup = fast back-to-back enable md 4 74 pci 66 mhz enable pulldown = 66 mhz pci disable pullup = 66 mhz pci enable md[ 6 : 5 ] 76-75 reference clock select 00 = 100 mhz 01 = 25mhz 10 = 150mhz 11 = 75mhz (default) md 7 77 reserved reserved table 2-5 power and ground pins symbol tqfp pin # type description gnda 7,9,12,16,18,21,25 gnd analog ground vss 41,48,76,81,92,107,113,123 gnd digital ground vdda (1.8 v) 4,8,13,17 pwr power supply to analog i/o?s vddc (1.8v) 47,80,112, pwr power supply for core vddio (3.3v) 28,40,75,91,106,122 pwr power supply for i/o drivers vddp 22,23 pwr power supply for pll
INIC-1622 data sheet confidential 7 section 3 address mapping summary 3.1 configuration spaces address map the configuration space is a contiguous block of 256 bytes accessible from the pci bus. for pci accesses to the configuration space, one of ad[31:11] is connected to pin pidsel and ad[10:8] = 000b. the lower 64 bytes of the configuration space is the predefined header. the next 32 bytes are INIC-1622 spe- cific. note : (ns) indicates not supported. 31 24 23 16 15 08 07 00 device id vendor id 00h status command 04h base class sub class prog. interface revision id 08h bist (ns) header type latency timer cache line size 0ch base address 0 (ata command-block registers for channel 0) 10h base address 1 (ata control-block registers for channel 0) 14h base address 2 (ata command-block registers for channel 1) 18h base address 3 (ata control-block registers for channel 1) 1ch base address 4 (ata bus master i/o registers) 20h base address 5 (ata bus master memory mapped registers) 24h reserved 28h subsystem id subsystem vendor id 2ch expansion rom base address 30h reserved capabilities pointer 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch reserved addresses 40h through d8h. 40-d8h power management capabilities next item pointer capabilities id dch pm data pm bridge support power management control/status e0h manufacture?s id f8h confidential
8 confidential INIC-1622 data sheet address mapping summary section 3 3.2 ata shadow registers these registers are accessible t hrough i/o space only. 3.2.1 command-block register command-block register for all except the packet and service commands are accessible through i/o base0 for channel 0 and base2 for channel 1. 3.2.2 control-block register control-block register for all except the packet and service commands are accessible through i/o base1 for channel 0 and base3 for channel 1. 3.2.3 register for the packet and service commands packet and service commands are accessible through i/o base0 for channel 0 and base2 for channel 1. 31 24 23 16 15 08 07 00 sector number sector count error/features data port 00h status/command device/head cylinder high cylinder low 04h 31 24 23 16 15 08 07 00 00h alt. status/control 04h 31 24 23 16 15 08 07 00 - - error/features data port 00h status/command device select byte count high byte count low 04h
section 3 address mapping summary INIC-1622 data sheet confidential 9 3.3 i/o & memory mapped registers address map 3.3.1 page 0 registers these registers are accessible through both i/o base4 and memory base. 31 24 23 16 15 08 07 00 lba low 0 sector cnt 0 err/features 0 pio data 0 00h stat/cmd 0 dev/head 0 lba high 0 lba mid 0 04h prd control 0 intr. mask 0 intr. stat 0 alt stat/ctrl 0 08h prd address 0 0ch prd total transfer length 0 10h idma status 0 idma control 0 14h cpb lookup table address 0 18h reply ff count 0 reply ff queue 0 post ff count 0 post ff queue 0 1ch sstatus 0 20h serror 0 24h scontrol 0 28h sactive 0 2ch 30h 34h scratch 38h rom data port rom addr 2 rom addr 1 rom addr 0 3ch lba low 1 sector cnt 1 err/features 1 pio data 1 40h stat/cmd 1 dev/head 1 lba high 1 lba mid 1 44h prd control 1 intr. mask 1 intr. stat 1 alt stat/ctrl 0 48h prd address 1 4ch prd total transfer length 1 50h idma status 1 idma control 1 54h cpb lookup table address 1 58h reply ff count 1 reply ff queue 1 post ff count 1 post ff queue 1 5ch sstatus 1 60h serror 1 64h scontrol 1 68h sactive 1 6ch - - - 70h 74h scratch 78h global status global control 7ch reserved 80-bbh global interrupt mask global interrupt status bch reserved c0-fbh reserved nvram port reserved reserved fch
10 confidential INIC-1622 data sheet address mapping summary section 3 3.3.2 page 1 registers these registers are accessible through both i/o base4 and memory base. 31 24 23 16 15 08 07 00 tp_debug0 00h lk_debug0 04h dcxa0 08h reserved 0ch dcxc0 10h reserved fflag0 14h fpdma_sm_cs0 aprd_sm_cs0 idma_sm_cs0 18h reserved 1ch phy_debug0 20h reserved 24-37h phy_ctl0 38h sspll feedback div. sspll input div. 3ch tp_debug1 40h lk_debug1 44h dcxa1 48h reserved 4ch dcxc1 50h reserved fflag1 54h fpdma_sm_cs1 aprd_sm_cs1 idma_sm_cs1 58h reserved 5ch phy_debug1 60h reserved 64-77h phy_ctl1 78h global status global control 7ch reserved 84-bbh reserved sspll pll loop sspll modulation ctrl. bch reserved c0-ffh
section 3 address mapping summary INIC-1622 data sheet confidential 11 3.4 command parameter blocks (cpb) structure definition the command parameter blocks (cpb) structure definition is shown in the table below. 3.5 physical region descriptor ( prd ) structure definition this register reflects the current physical pointer to a prd list in the system memory. the descriptor table should be aligned on a dword boundary and cannot cross a 65,536 boundary in memory. 3.6 summary of supported pci commands 31 24 23 16 15 08 07 00 control flags ata status ata error response flags 00h s s s s s s s s total transfer length 04h first prd pointer (qword aligned) 08h reserved 0ch mirror control ata device/head ata ex. feature ata feature 10h ata ex. sector num- ber ata sector number ata ex. sector count ata sector count 14h ata ex. cylinder high ata cylinder high ata ex. cylinder low ata cylinder low 18h slave ata status slave ata error ata control ata command 20h 31 24 23 16 15 08 07 00 physical memory address 00h control flags reserved transfer length 04h cbe[3:0] command master / slave mode 0000 interrupt acknowledge - 0001 special cycle - 0010 i/o read slave 0011 i/o write slave 0100 reserved - 0101 reserved - 0110 memory read master/ slave 0111 memory write master/ slave 1000 reserved - 1001 reserved - 1010 configuration read slave 1011 configuration write slave 1100 memory read multiple master 1101 dual address cycle master 1110 memory read line master 1111 memory write and invalidate master
12 confidential INIC-1622 data sheet address mapping summary section 3 this page is intentially left blank.
INIC-1622 data sheet confidential 13 section 4 register descriptions 4.1 configuration space register descriptions these registers can be read from or written to from the pci interface when idsel is asserted, ad[1:0] = 00b, ad[10:8] = 000b and the pci command indicated on cbe[3:0]# = 1010b or 1011b. 00h vendor id (pvid[1:0]) this register identifies ?initio? as the vendor of this device. it will always read ?1101h?. the contents of these registers can be modified just after a power on reset. the new contents of this register will be fetched by on chip hardware from the external nvram. for more details, please see bit lddflt in register gstat . bit(s) rw reset acronym definition 15:0 r 1101h (vid15-0) always reads 1101h. 02h device id (pdid[1:0]) this register indicates the device identification number. the device identification number for this device is ?1622h?. the contents of these registers can be modified just after a power on reset. the new contents of this register will be fetched by on chip hardware from the external nvram. for more details, please see bit lddflt in register gstat . bit(s) rw reset acronym definition 31:16 r 16 2 2h (did15-0) always reads 1622h. pvid1 pvid0 15 vid15 = 0 07 vid07 = 0 14 vid14 = 0 06 vid06 = 0 13 vid13 = 0 05 vid05 = 0 12 vid12 = 1 04 vid04 = 0 11 vid11 = 0 03 vid03 = 0 10 vid10 = 0 02 vid02 = 0 09 vid09 = 0 01 vid01 = 0 08 vid08 = 1 00 vid00 = 1 pdid1 pdid0 31 did15 = 0 23 did07 = 0 30 did14 = 0 22 did06 = 0 29 did13 = 0 21 did05 = 1 28 did12 = 1 20 did04 = 0 27 did11 = 0 19 did03 = 0 26 did10 = 1 18 did02 = 0 25 did09 = 1 17 did01 = 1 24 did08 = 0 16 did00 = 0 confidential
14 confidential INIC-1622 data sheet register descriptions section 4 04h command (pcmd[1:0]) the command register provides coarse control over INIC-1622?s ability to generate and respond to pci cycles. when a ?00h? is written to this register, the INIC-1622 is logically disconnected from the pci bus for all accesses except configuration cycles. bit(s) rw reset acronym definition 15-11 rw 0 (rsvd) always reads 0. 10 rw 0 (inten) interrupt enable: this bit enables the generation of intx signal whenever there is an interrupt pending. 09 rw 0 (fbtben) master fast back-to-back: this feature is not supported. always reads 0. 08 rw 0 (serren) serr# enable: when set will enable the serr# signal to be asserted when an address parity error is detected on the ad, cbe#, par, and par64 signal lines during the address phase. when reset, the serr# sig- nal will not be driven if these above conditions occur. 07 rw 0 (wctlen) wait control enable: this feature is not supported. always reads 0. 06 rw 0 (peresen) perr# enable: when set will enable the perr# signal to be asserted when a data parity error is detected on the ad, cbe#, par, and par64 signal lines during the address phase and will set the data parity error detected bit in status1 register in the configuration space. when reset the data parity error detected bit is set in status1 register in the con- figuration space, if a parity error is detected during the address phase, but the perr# signal is not asserted. 05 rw 0 (vgaen) vga snoop enable: this feature is not supported. always reads 0. 04 rw 0 (mwrien) memory write and invalidate command enable: when set will enable the device to issue memory write and invalidate com- mands. when reset the device will issue memory write commands. 03 rw 0 (specyc) special cycle enable: this feature is not supported. always reads 0. 02 rw 0 (busmen) bus master enable: when set, this bit enables the bus master func- tion of the host adapter. when reset, it disables the host from generating any pci requests. 01 rw 0 (mspaen) memory space enable: when set, enables the device to respond to memory space transactions. when reset, disables the devices ability to respond to memory space transactions. 00 rw 0 (ispaen) i/o space enable: when set, enables the device to respond to i/o space transactions. when reset, disables the devices ability to respond to i/ o space transactions. pcmd1 pcmd0 15 rsvd 07 wctlen = 0 14 rsvd 06 peresen 13 rsvd 05 vgaen = 0 12 rsvd 04 mwrien 11 rsvd 03 specyc = 0 10 inten 02 busmen 09 fbtben = 0 01 mspaen 08 serren 00 ispaen
section 4 register descriptions INIC-1622 data sheet confidential 15 06h status (pstus[1:0]) the status register is used to record status information for pci bus related events. to reset any writeable bit, write that bit value with a 1 . bit(s) rw reset acronym definition 31 rw 0 (dperr) detected parity error status: when set, it indicates that the device detected a 36 bit parity error during the address phase or write data phase as a target, or a parity error during a read data phase as a master. 30 rw 0 (sserr) signaled system error status: when set, it indicates that the device generated a system error on the serr# line. 29 rw 0 (rmabt) received master abort status: when set it indicates that the device as a bus master received a master abort. 28 rw 0 (trabt) received target abort status: when set, it indicates that the device as a bus master received a target abort. 27 rw 0 (stabt) signaled target abort status: when set, it indicates to the master that the device as a target is unable to respond due to some fatal condition. 26-25 rw 01 (devsel[01:00]) device select timing status: device asserts devsel# signal in the medium timing mode for any bus command, i.e., two clocks after frame# is asserted. 24 rw 0 (dperd) master data parity error detected: when set, this bit indi- cates that the device as a bus master either observed perr# asserted, or the bus master asserted perr# and the parity error response bit was enabled in the command register in the configuration space. 23 rw 0 (fbtbc) fast back to back status: the device as a target is not capable of fast back to back transactions. with the configuration bit md3, fbtbc can be enabled or disabled. 22 rw 0 reserved reserved . always reads 0. 21 rw 0 (m66c) 66mhz capable status: the device is incapable of running at 66mhz. with the configuration bit md4, m66c can be enabled or dis- abled. 20 rw 1 (caplst) capabilities list: indicates if the device implements the pointer for a new capabilities link list at offset 34h. always reads 1. 19 rw 0 (intstat) interrupt status: indicates that an interrupt is pending. 18-16 rw 0 reserved reserved . always reads 0. pstus1 pstus0 31 dperr 23 fbtbc 30 sserr 22 rsvd 29 rmabt 21 m66c 28 rtabt 20 caplst 27 stabt 19 intstat 26 devsel01 = 0 18 rsvd 25 devsel00 = 1 17 rsvd 24 dperd 16 rsvd
16 confidential INIC-1622 data sheet register descriptions section 4 08h device revision id (prid) this register identifies the revision level of the device. it indicates different steppings of the device. for the first step of this device it will read as a 01h. subsequent steps of the device reflect an increment of 1. bit(s) rw reset acronym definition 07-00 r 01h (rid[07:00]) revision id: indicates the device step number. every subsequent revi- sion step reflects an increment by 1 with respect to the previous revision step number. 09h programming interface (ppi) this register identifies the programming interface the device supports. for idma mode, it always reads 00h. note : the contents of these registers can be modified just after a power on reset. the new contents of this register will be fetched by on chip hardware from the external nvram. for more details, please see bit lddflt in register gstat. bit(s) rw reset acronym definition 15-08 r 0 0h ( pi[07:00]) programming interface prid 07 rid07 06 rid06 05 rid05 04 rid04 03 rid03 02 rid02 01 rid01 00 rid00 prid 15 pi07 = 0 14 pi06 = 0 13 pi05 = 0 12 pi04 = 0 11 pi03 = 0 10 pi02 = 0 09 pi01 = 0 08 pi00 = 0
section 4 register descriptions INIC-1622 data sheet confidential 17 0ah sub class (psc) this register identifies the device as a serial ata type device. it always reads 06h . note : the contents of these registers can be modified just after a power on reset. the new contents of this register will be fetched by on chip hardware from the external nvram. for more details, please see bit lddflt in register gstat. bit(s) rw reset acronym definition 23-16 r 0 6h (sc[07:00]) sub class: this register defines the sub class of the device. the default value of this register is ?06h? meaning serial ata d evice. 0bh base class (pbc) this register identifies the device as a mass storage controller. it always reads 01h. note : the contents of these registers can be modified just after a power on reset. the new contents of this register will be fetched by on chip hardware from the external nvram. for more details, please see bit lddflt in register gstat. bit(s) rw reset acronym definition 31-24 r 01 h (bc[07:00]) base class: this register defines the base class of the device. it always reads ?01h? indicating that the device is a mass storage controller. sc 23 sc07 = 0 22 sc06 = 0 21 sc05 = 0 20 sc04 = 0 19 sc03 = 0 18 sc02 = 1 17 sc01 = 1 16 sc00 = 0 sc 31 bc07 = 0 30 bc06 = 0 29 bc05 = 0 28 bc04 = 0 27 bc03 = 0 26 bc02 = 0 25 bc01 = 0 24 bc00 = 1
18 confidential INIC-1622 data sheet register descriptions section 4 0ch cache line size (pcls) this register specifies the system cache line size in 32-bit words only if the memory write and invalidate enable bit is set to a 1 in the command register. in this case the device will issue either memory write and invalidate, memory read line or memory read multiple commands. if this bit is reset then the device will issue either memory write or memory read commands. the device uses the value stored in the cache line size register to determine when to issue cache commands at cache line boundries. bit(s) rw reset acronym definition 07-00 rw 01 h (cls[07:00]) cache line size: the value stored in the cache line register deter- mines when the INIC-1622 issues cache line referenced commands based on the number of data bytes stored in the data fifo internal to the chip. 0dh latency timer (plt) this register specifies the master latency timer value for a pci master when the device is on the pci bus. the least three significant bits are hard wired to 0, resulting in a pclk granularity of 8 pclk?s. bit(s) rw reset acronym definition 15-11 r w 0 (lt[07:03]) latency timer [07:03]: indicates the bus master latency period in pclk time units. 10-08 r 0 (lt[02:00]) latency timer [02:00]: these 3 bits always read 0, setting the granu- larity to 8 pclk?s. pcls 07 cls07 06 cls06 05 cls05 04 cls04 03 cls03 02 cls02 01 cls01 00 cls00 plt 15 lt07 14 lt06 13 lt05 12 lt04 11 lt03 10 lt02 = 0 09 lt01 = 0 08 lt00 = 0
section 4 register descriptions INIC-1622 data sheet confidential 19 0eh header type (phdt) this register identifies the layout of bytes beginning at offset 10h in the pci configuration space. in addition, this reg- ister specifies whether the device is a single or multi function device. bit(s) rw reset acronym definition 23 r 0 (mfdev) multi function status: this device is a single function device. it always reads 0. 22-16 r 0 (hdt[06:00]) header type [06:00]: these 5 bits always read 0, to indicate the lay- out of bytes 10h-3fh in the configuration space . 0fh built in self test (bist) this register is used to control the invocation of a pci device?s bist and to report the status of bist. this device does not support bist and always reads 0. bit(s) rw reset acronym definition 31-24 r 0 (bist[31:24]) built in self test: this device does not support bist. it always reads 0. phdt 23 mfdev = 0 22 hdt06 = 0 21 hdt05 = 0 20 hdt04 = 0 19 hdt03 = 0 18 hdt02 = 0 17 hdt01 = 0 16 hdt00 = 0 pbist 31 bist07 = 0 30 bist06 = 0 29 bist05 = 0 28 bist04 = 0 27 bist03 = 0 26 bist02 = 0 25 bist01 = 0 24 bist00 = 0
20 confidential INIC-1622 data sheet register descriptions section 4 10h base address 0 (pbase0) this register allows a pci devices?s i/o functions to be dynamically mapped into a system?s i/o address space. bit(s) rw reset acronym definition 31-08 rw 00h (baio[31:08]) i/o base address [31:08]: these are read/write bits allowing the sys- tem to access channel 0 command b lock registers. 07-02 r 00h (baio[07:02]) reserved: these bits always read 0. 01 r 0 reserved reserved: this bit always reads 0. 00 r 1 (iospind) i/o address space indicator: this bit always reads 1 indicating that the device?s base address register is requesting i/o space. 14h base address 1 (pbase1) this register allows a pci devices?s i/o functions to be dynamically mapped into a system?s i/o address space. bit(s) rw reset acronym definition 31-08 rw 00h (baio[31:08]) i/o base address [31:08]: these are read/write bits allowing the sys- tem to access channel 0 control block registers. 07-02 r 00h (baio[07:02]) reserved: these bits always read 0. 01 r 0 reserved reserved: this bit always reads 0. 00 r 1 (iospind) i/o address space indicator: this bit always reads 1 indicating that the device?s base address register is requesting i/o space. pbase0 31 baio31 23 baio23 15 baio15 07 baio07 = 0 30 baio30 22 baio22 14 baio14 06 baio06 = 0 29 baio29 21 baio21 13 baio13 05 baio05 = 0 28 baio28 20 baio20 12 baio12 04 baio04 = 0 27 baio27 19 baio19 11 baio11 03 baio03 = 0 26 baio26 18 baio18 10 baio10 02 baio02 = 0 25 baio25 17 baio17 09 baio09 01 rsvd = 0 24 baio24 16 baio16 08 baio08 00 iospind = 1 pbase1 31 baio31 23 baio23 15 baio15 07 baio07 = 0 30 baio30 22 baio22 14 baio14 06 baio06 = 0 29 baio29 21 baio21 13 baio13 05 baio05 = 0 28 baio28 20 baio20 12 baio12 04 baio04 = 0 27 baio27 19 baio19 11 baio11 03 baio03 = 0 26 baio26 18 baio18 10 baio10 02 baio02 = 0 25 baio25 17 baio17 09 baio09 01 rsvd = 0 24 baio24 16 baio16 08 baio08 00 iospind = 1
section 4 register descriptions INIC-1622 data sheet confidential 21 18h base address 2 (pbase2) this register allows a pci devices?s i/o functions to be dynamically mapped into a system?s i/o address space. bit(s) rw reset acronym definition 31-08 rw 00h (baio[31:08]) i/o base address [31:08]: these are read/write bits allowing the sys- tem to access channel 1 command b lock registers. 07-02 r 00h (baio[07:02]) reserved: these bits always read 0. 01 r 0 reserved reserved: this bit always reads 0. 00 r 1 (iospind) i/o address space indicator: this bit always reads 1 indicating that the device?s base address register is requesting i/o space. 1ch base address 3 (pbase3) this register allows a pci devices?s i/o functions to be dynamically mapped into a system?s i/o address space. bit(s) rw reset acronym definition 31-08 rw 00h (baio[31:08]) i/o base address [31:08]: these are read/write bits allowing the sys- tem to access channel 1 control block registers. 07-02 r 00h (baio[07:02]) reserved: these bits always read 0. 01 r 0 reserved reserved: this bit always reads 0. 00 r 1 (iospind) i/o address space indicator: this bit always reads 1 indicating that the device?s base address register is requesting i/o space. pbase2 31 baio31 23 baio23 15 baio15 07 baio07 = 0 30 baio30 22 baio22 14 baio14 06 baio06 = 0 29 baio29 21 baio21 13 baio13 05 baio05 = 0 28 baio28 20 baio20 12 baio12 04 baio04 = 0 27 baio27 19 baio19 11 baio11 03 baio03 = 0 26 baio26 18 baio18 10 baio10 02 baio02 = 0 25 baio25 17 baio17 09 baio09 01 rsvd = 0 24 baio24 16 baio16 08 baio08 00 iospind = 1 pbase3 31 baio31 23 baio23 15 baio15 07 baio07 = 0 30 baio30 22 baio22 14 baio14 06 baio06 = 0 29 baio29 21 baio21 13 baio13 05 baio05 = 0 28 baio28 20 baio20 12 baio12 04 baio04 = 0 27 baio27 19 baio19 11 baio11 03 baio03 = 0 26 baio26 18 baio18 10 baio10 02 baio02 = 0 25 baio25 17 baio17 09 baio09 01 rsvd = 0 24 baio24 16 baio16 08 baio08 00 iospind = 1
22 confidential INIC-1622 data sheet register descriptions section 4 20h base address 4 (pbase4) this register allows a pci devices?s i/o functions to be dynamically mapped into a system?s i/o address space. bit(s) rw reset acronym definition 31-08 rw 00h (baio[31:08]) i/o base address [31:08]: these are read/write bits allowing the sys- tem to access i dma i/o registers. 07-02 r 00h (baio[07:02]) reserved: these bits always read 0. 01 r 0 reserved reserved: this bit always reads 0. 00 r 1 (iospind) i/o address space indicator: this bit always reads 1 indicating that the device?s base address register is requesting i/o space. 24h memory base address (pbam) this register allows a pci devices?s memory functions to be dynamically mapped into a system?s memory address space. these are the lower 32 bits of the memory space base address of a 64-bit address space. bit(s) rw reset acronym definition 31-08 rw 0 0h (bam0[31:12]) memory base address [31:12]: these are the 32 read/write address bits allowing the system to map the device into a 32-bit address space. 07-04 r 0 h (bam0[11:04]) memory base address [11:04]: these bits always read 0 indicating a request for a 4 kbyte block of memory address space. 03 r 0 ( prefetch) prefetchable: this bit always reads 0, indicating that its memory is not prefetchable. 02-01 r 00b (memtyp[01:00]) memory type: these bit always read 00b, indicating that the device?s base address register is 32 bits and is requesting a memory space base address anywhere within the 32-bit memory space. 00 r 0 (mspind) memory address space indicator: this bit always reads 0 indicating that the device is requesting memory space. pbase4 31 baio31 23 baio23 15 baio15 07 baio07 = 0 30 baio30 22 baio22 14 baio14 06 baio06 = 0 29 baio29 21 baio21 13 baio13 05 baio05 = 0 28 baio28 20 baio20 12 baio12 04 baio04 = 0 27 baio27 19 baio19 11 baio11 03 baio03 = 0 26 baio26 18 baio18 10 baio10 02 baio02 = 0 25 baio25 17 baio17 09 baio09 01 rsvd = 0 24 baio24 16 baio16 08 baio08 00 iospind = 1 pbam 31 bam031 23 bam023 15 bam015 07 bam007 = 0 30 bam030 22 bam022 14 bam014 06 bam006 = 0 29 bam029 21 bam021 13 bam013 05 bam005 = 0 28 bam028 20 bam020 12 bam012 04 bam004 = 0 27 bam027 19 bam019 11 bam011 = 0 03 prefetch = 0 26 bam026 18 bam018 10 bam010 = 0 02 memtyp1 = 0 25 bam025 17 bam017 09 bam009 = 0 01 memtyp0 = 0 24 bam024 16 bam016 08 bam008 = 0 00 mspind = 1
section 4 register descriptions INIC-1622 data sheet confidential 23 2ch sub system vendor id, sub system id (psubvid[1:0], psubid[1:0]) the subsystem vendor id and subsystem id registers are used to uniquely identify the add-in board or subsystem where the pci device resides. they provide a way for add-in card vendors to distinguish their cards from one another even when the cards have the same pci controller installed. n ote: the contents of these registers can be modified just after a power on reset. the new contents of this register will be fetched by on chip hardware from the external nvram. for more details, please see bit lddflt in register gstat. bit(s) rw reset acronym definition 31-16 r 1622h ( psubid[1:0]) subsystem id: default always reads 1622h. 15-00 r 1101h ( psubvid[1:0]) subsystem vendor id: default always reads 1101h. 30h expansion rom base address (pbar) this register allows a pci device?s expansion rom to be mapped into a system?s physical address space. a maxi- mum of 512k bytes rom space is supported. bit(s) rw reset acronym definition 31-19 rw 00h (bar[31:19]) expansion rom base address [31:19]: these are read/write bits allowing the system to map in increments of 512k bytes of expansion rom space. base address may share a decoder with the i/o and memory base address register, device independent software should not access any other base address register of this device while the expansion rom decode for this device is enabled. 07-02 r 00h (bar[18:11]) expansion rom base address [18:11]. always read 0 to set the maximum size of the expansion rom device to be 512 kbytes. 10-01 r 0 0h reserved reserved: this bit always reads 0. psubid[1:0] psubvid[1:0] 31 psubid15 = 0 23 psubid07 = 0 15 psubvid15 = 0 07 psubvid07 = 0 30 psubid14 = 0 22 psubid06 = 0 14 psubvid14 = 0 06 psubvid06 = 0 29 psubid13 = 0 21 psubid05 = 1 13 psubvid13 = 0 05 psubvid05 = 0 28 psubid12 = 1 20 psubid04 = 0 12 psubvid12 = 1 04 psubvid04 = 0 27 psubid11 = 0 19 psubid03 = 0 11 psubvid11 = 0 03 psubvid03 = 0 26 psubid10 = 1 18 psubid02 = 0 10 psubvid10 = 0 02 psubvid02 = 0 25 psubid09 = 1 17 psubid01 = 1 09 psubvid09 = 0 01 psubvid01 = 0 24 psubid08 = 0 16 psubid00 = 0 08 psubvid08 = 1 00 psubvid00 = 1 pbar 31 bar31 23 bar23 15 bar15 = 0 07 rsvd = 0 30 bar30 22 bar22 14 bar14 = 0 06 rsvd = 0 29 bar29 21 bar21 13 bar13 = 0 05 rsvd = 0 28 bar28 20 bar20 12 bar12 = 0 04 rsvd = 0 27 bar27 19 bar19 11 bar11 = 0 03 rsvd = 0 26 bar26 18 bar18 = 0 10 rsvd = 0 02 rsvd = 0 25 bar25 17 bar17 = 0 09 rsvd = 0 01 rsvd = 0 24 bar24 16 bar16 = 0 08 rsvd = 0 00 exromen
24 confidential INIC-1622 data sheet register descriptions section 4 00 rw 0 (exromen) expansion rom decode enable: when set it enables the decode of the expansion rom within system memory address space. bit 1 of this device?s command register, the memory space control bit, has prece- dence over this bit. it must be set to a value of 1 for this bit to enable the expansion rom address decode. 34h capabilities pointer (capptr) this register is the pointer for the pci power management capability offset. bit(s) rw reset acronym definition 07-00 r dch (capptr[07:00]) capabilities pointer: this pointer points to the pci power man- agement capability offset. 3ch interrupt line select (pil) this register identifies which interrupt request line of a system interrupt controller the pci device?s interrupt line is connected to. note that these encodings specify the physical pin on the system interrupt controller that the interrupt line is connected to. these encodings do not specify the interrupt vector that is generated by the interrupt controller. bit(s) rw reset acronym definition 07-00 rw 0 (il[07:00]) interrupt line value: values between 00h:feh is the interrupt line number that the device is connected to. a value of ffh indicates that the device?s interrupt line is not connected to a system interrupt controller. capptr 07 capptr0 7 = 1 06 capptr0 6 = 1 05 capptr0 5 = 0 04 capptr0 4 = 1 03 capptr0 3 = 1 02 capptr0 2 = 1 01 capptr0 1 = 0 00 capptr0 0 = 0 pil 07 il07 06 il06 05 il05 04 il04 03 il03 02 il02 01 il01 00 il00
section 4 register descriptions INIC-1622 data sheet confidential 25 3dh interrupt pin select (pip) this register identifies which interrupt pin, inta# through intd#, a device function uses. this register assists in the proper initialization of the interrupt line register. bit(s) rw reset acronym definition 15-08 r 01h (ip[07:00]) interrupt pin: this register always reads 01h indicating that the device uses interrupt pin i nta#. 3eh minimum grant (pmg) this register specifies the burst period (assuming a clock rate of 33mhz) required by the device. the value is speci- fied in increments of 250ns (0.25us). bit(s) rw reset acronym definition 23-16 r 00h (mg[07:00]) minimum grant value: always reads 0. pip 15 ip07 = 0 14 ip06 = 0 13 ip05 = 0 12 ip04 = 0 11 ip03 = 0 10 ip02 = 0 09 ip01 = 0 08 ip00 = 1 pmg 23 mg07 = 0 22 mg06 = 0 21 mg05 = 0 20 mg04 = 0 19 mg03 = 0 18 mg02 = 0 17 mg01 = 0 16 mg00 = 0
26 confidential INIC-1622 data sheet register descriptions section 4 3fh maximum latency (pml) this register specifies how often (assuming a clock rate of 33mhz) the device needs to gain access to the pci bus. the value is specified in 250ns increments (0.25us). bit(s) rw reset acronym definition 31-24 r 00h (ml[07:00]) maximum latency value: always reads 0. dch capability id (cid) bit(s) rw reset acronym definition 07-00 r 01h (cid) capability id: indicates that the device s upports p ci pms . ddh next item pointer (nip) bit(s) rw reset acronym definition 07-00 r 00h (nip) next item pointer: the next capability points to the next capability; 00h indicates the end of the link list of capabilities. pml 31 ml07 = 0 30 ml06 = 0 29 ml05 = 0 28 ml04 = 0 27 ml03 = 0 26 ml02 = 0 25 ml01 = 0 24 ml00 = 0 cid 07 cid7 = 0 06 cid6 = 0 05 cid5 = 0 04 cid4 = 0 03 cid3 = 0 02 cid2 = 0 01 cid1 = 0 00 cid0 = 1 nip 07 nip7 06 nip6 05 nip5 04 nip4 03 nip3 02 nip2 01 nip1 00 nip0
section 4 register descriptions INIC-1622 data sheet confidential 27 deh power management capabilities (pmc) bit(s) rw reset acronym definition 15-14 r 0 reserved reserved: always reads 0. 13 r 1 (pmc13) pmc [13]: this bit when set to one indicates that the id ma may assert pme# from the d2 state if the signal uintrq (unsolicited interrupt) is asserted on either channel. 11-12 r 0 reserved reserved: always reads 0. 10 r 1 (pmc10) pmc [10]: this bit when set to one indicates that id ma supports the d2 (standby) state. 09-04 r 0 reserved reserved: always reads 0. 03 r 1 (pmc03) pmc [03]: this bit when set to one indicates that the id ma requires a pci clock to assert pme#. 02-00 r 010b (pmc00/01/02) pmc [02/01/00]: these bits when set to 010b indicate that the id ma complies with version 1.1 of the p ci pms . e0h power management control/status (pmcs) bit(s) rw reset acronym definition 15 rw 0 (pmcs[15]) pmcs [15]: indicates whether pme# can be asserted from power state d3-cold. fixed to zero indicating that the id ma does not support pme# assertion from the d3-cold state. 14-09 r 0 0h reserved reserved: always reads 0. 08 rw 0 (pmcs[08]) pme# enable: controls the enable and disable of pme#. when this bit is set to one, pme# is enabled. when this bit is cleared to zero, pme# is disabled. pmc 15 pmc15 = 0 07 pmc07 = 0 14 pmc14 = 0 06 pmc06 = 0 13 pmc13 = 1 05 pmc05 = 0 12 pmc12 = 0 04 pmc04 = 0 11 pmc11 = 0 03 pmc03 = 1 10 pmc10 = 1 02 pmc02 = 0 09 pmc09 = 0 01 pmc01 = 1 08 pmc08 = 0 00 pmc00 = 0 pmcs 15 pmcs15 07 rsvd = 0 14 rsvd = 0 06 rsvd = 0 13 rsvd = 0 05 rsvd = 0 12 rsvd = 0 04 rsvd = 0 11 rsvd = 0 03 rsvd = 0 10 rsvd = 0 02 rsvd = 0 09 rsvd = 0 01 pmcs01 08 pmcs08 00 pmcs00
28 confidential INIC-1622 data sheet register descriptions section 4 07-02 r 0 0h reserved reserved: always reads 0. 01-00 rw 0 0 (pmcs[01/00]) pmc state control: power management state control bits. e2h power management bridge support extension (bse) bit(s) rw reset acronym definition 07-00 r 0 0h (bse) bridge support extension e3h power management data (pmdr) bit(s) rw reset acronym definition 07-00 r 0 0h (pmdr) id ma power management data f8h manufacture?s id (mftid) bit(s) rw reset acronym definition 31-00 r 1101 (mftid[31:00]) manufacture?s id: always reads 1101 1101h. 1101 bse 07 bse07 = 0 06 bse06 = 0 05 bse05 = 0 04 bse04 = 0 03 bse03 = 0 02 bse02 = 0 01 bse01 = 0 00 bse00 = 0 pmdr 07 pmdr07 = 0 06 pmdr06 = 0 05 pmdr05 = 0 04 pmdr04 = 0 03 pmdr03 = 0 02 pmdr02 = 0 01 pmdr01 = 0 00 pmdr00 = 0 mftid 31 mftid31 23 mftid23 15 mftid15 07 mftid07 30 mftid30 22 mftid22 14 mftid14 06 mftid06 29 mftid29 21 mftid21 13 mftid13 05 mftid05 28 mftid28 20 mftid20 12 mftid12 04 mftid04 27 mftid27 19 mftid19 11 mftid11 03 mftid03 26 mftid26 18 mftid18 10 mftid10 02 mftid02 25 mftid25 17 mftid17 09 mftid09 01 mftid01 24 mftid24 16 mftid16 08 mftid08 00 mftid00
section 4 register descriptions INIC-1622 data sheet confidential 29 4.2 page 0 i/o & memory mapped register descriptions these registers are accessible through the first page of pci base address space 4 using io cycles or pci base address space 5 by memory cycles. the register page is selected through gctrl (offset 7c) bit 15. when this bit is cleared, page 0 is selected. base4/5 + 00h (ch 0 ) ata data port (adata) base4/5 + 40h (ch 1 ) reset: hw reset this 16 bit register provides a data port for ata pio data transfer. an 8-bit write to address 00 will perform a write to the lower 8 bits of ata data. a 16-bit write to address 00 will perform a word write to the entire 16 bits of ata data. bit(s) rw reset acronym definition 15:00 rw 00h (adata[15:00]) ata data: ata pio transfer data port. base4/5 + 01h (ch 0 ) ata error/feature (aerr/afeat) base4/5 + 41h (ch 1 ) reset: hw reset this register is a dual purpose ata register. when write, it is the ata features register whose function is command dependent. when read, it serves as the ata error register which reports the status of the current command. bit(s) rw reset acronym definition 15:08 w 00h (afeat[07:00]) ata features: write only and the content is command dependent. 15:08 r 00h (aerr[07:00]) ata error: read only and the content is command dependent. adata1 adata0 15 adata15 07 adata07 14 adata14 06 adata06 13 adata13 05 adata05 12 adata12 04 adata04 11 adata11 03 adata03 10 adata10 02 adata02 09 adata09 01 adata01 08 adata08 00 adata00 afeat aerr 15 afeat07 15 aerr07 14 afeat06 14 aerr06 13 afeat05 13 aerr05 12 afeat04 12 aerr04 11 afeat03 11 aerr03 10 afeat02 10 aerr02 09 afeat01 09 aerr01 08 afeat00 08 aerr00
30 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 02h (ch 0 ) ata sector count (aseccnt) base4/5 + 42h (ch 1 ) reset: hw reset this register corresponds to the ata sector count register. bit(s) rw reset acronym definition 23:16 rw 00h (aseccnt[07:00]) ata sector count: the content is command dependent. base4/5 + 03h (ch 0 ) ata lba low (albal) base4/5 + 43h (ch 1 ) reset: hw reset this register corresponds to the ata lba low register. bit(s) rw reset acronym definition 31:24 rw 00h (albal[07:00]) ata lba low: the content is command dependent. aseccnt 23 aseccnt07 22 aseccnt06 21 aseccnt05 20 aseccnt04 19 aseccnt03 18 aseccnt02 17 aseccnt01 16 aseccnt00 albal 31 albal07 30 albal06 29 albal05 28 albal04 27 albal03 26 albal02 25 albal01 24 albal00
section 4 register descriptions INIC-1622 data sheet confidential 31 base4/5 + 04h (ch 0 ) ata lba mid (albam) base4/5 + 44h (ch 1 ) reset: hw reset this register corresponds to the ata lba mid register. bit(s) rw reset acronym definition 07:00 rw 0 0h (albam[07:00]) ata lba mid: the content is command dependent. base4/5 + 05h (ch 0 ) ata lba high (albah) base4/5 + 45h (ch 1 ) reset: hw reset this register corresponds to the ata lba high register. bit(s) rw reset acronym definition 15:08 rw 00h (albah[07:00]) ata lba high: the content is command dependent. albam 07 albam07 06 albam06 05 albam05 04 albam04 03 albam03 02 albam02 01 albam01 00 albam00 albah 15 albah07 14 albah06 13 albah05 12 albah04 11 albah03 10 albah02 09 albah01 08 albah00
32 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 06h (ch 0 ) ata device (adev) base4/5 + 46h (ch 1 ) reset: hw reset this register corresponds to the ata device register. bit(s) rw reset acronym definition 23:16 rw 00h (adev[07:00]) ata device: the content is command dependent. base4/5 + 07h (ch 0 ) ata status/command (acmd/astat) base4/5 + 47h (ch 1 ) reset: hw reset this register is a dual purpose ata register. when write, it is the ata command register. when read, it serves as the ata status register which reports the status of the current command. bit(s) rw reset acronym definition 31:24 w 00h (acmd[07:00]) ata command: write only and it contains the command code being sent to the device. 31:24 r 00h (astat[07:00]) ata status: read only and the content is device status. the content is updated to reflect the current state of the device and the progress of any command being executed. adev 23 adev07 22 adev06 21 adev05 20 adev04 19 adev03 18 adev02 17 adev01 16 adev00 acmd astat 31 acmd07 31 astat07 30 acmd06 30 astat06 29 acmd05 29 astat05 28 acmd04 28 astat04 27 acmd03 27 astat03 26 acmd02 26 astat02 25 acmd01 25 astat01 24 acmd00 24 astat00
section 4 register descriptions INIC-1622 data sheet confidential 33 base4/5 + 08h (ch 0 ) ata alternatestatus/control (actrl/aastat) base4/5 + 48h (ch 1 ) reset: hw reset this register is a dual purpose ata register. when write, it is the ata device control register. when read, it serves as the ata alternate status register which reports the status of the current command. bit(s) rw reset acronym definition 07:00 w 00h (actrl[07:00]) ata device control: write only it allows the host to software reset attached devices and to enable/disable intrq signals. both devices respond to a single write to this register. 07:00 r 00h (aastat[07:00]) ata alternate status: read only and it contains the same value as the status register at address 07h. actrl aastat 07 actrl07 07 aastat07 06 actrl06 06 aastat06 05 actrl05 05 aastat05 04 actrl04 04 aastat04 03 actrl03 03 aastat03 02 actrl02 02 aastat02 01 actrl01 01 aastat01 00 actrl00 00 aastat00
34 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 09h (ch 0 ) ata interrupt status (intstat) base4/5 + 49h (ch 1 ) reset: hw reset & channel reset this register contains the interrupt status of the corresponding sata channel. bit(s) rw reset acronym definition 15 r 0 (chintp) channel interrupt pending: this bit reflects the masked inter- rupt status of the sata channel. 14 r 0 reserved reserved: always reads 0. 13 r 0 (chqint) channel queue interrupt: channel reply fifo queue not empty interrupt. 12 r 0 (chuirq) channel unsolicited interrupt: channel unsolicited interrupt (ataint). 11 r 0 (ftlint) fatal error interrupt: fatal error interrupt. 10 r 0 (chcint) channel complete interrupt: channel complete interrupt. 09 r 0 (chon) sata channel on: sata channel detected a device being plugged in. 08 r 0 (choff) sata channel off: sata channel detected a device being unplugged. intstat 15 chintp 14 rsvd 13 chqint 12 chuirq 11 ftlint 10 chcint 09 chon 08 choff
section 4 register descriptions INIC-1622 data sheet confidential 35 base4/5 + 0ah (ch 0 ) ata mask interrupt status (mintstat) base4/5 + 4ah (ch 1 ) reset: hw reset this register is used to mask the corresponding sata channel interrupts. bit(s) rw reset acronym definition 23-22 r 0 reserved reserved: always reads 0. 21 rw 0 (mchqint) mask channel queue interrupt: mask channel reply fifo queue empty interrupt. 20 rw 0 (mchuirq) mask channel unsolicited interrupt: mask channel unso- licited interrupt. 19 r w 0 (mftlint) mask fatal error interrupt: mask channel fatal error inter- rupt. 18 rw 0 (mchcint) mask channel complete interrupt: mask channel complete interrupt. 17 rw 0 (mchon) mask sata channel on: mask sata channel detected a device being plugged in. 16 rw 0 (mchoff) mask sata channel off: mask sata channel detected a device being unplugged. mintstat 23 rsvd 22 rsvd 21 mchqint 20 mchuirq 19 mftlint 18 mchcint 17 mchon 16 mchoff
36 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 0bh (ch 0 ) physical region descriptor (prd) control (prdctl) base4/5 + 4bh (ch 1 ) reset: hw reset this register provides controls for prd modes of operations. bit(s) rw reset acronym definition 31 rw 0 ( dmaen) dma transfer enable : if set to 1, dma transfer is used. if cleared, pio transfer is used. 30-28 r 0 00b r eserved reserved: should return to zero on read. 27 rw 0 (dir) direction : this bit sets the direction of the bus master transfer. when clear, pci master reads are performed. when set to one, pci master writes are performed. 26-25 r 00b reserved reserved: should return to zero on read. 24 rw 0 (start/stop) bus master : bus master operation of the adapter is enabled by setting this bit to one. master operation may be halted by clearing this bit to zero. all state information is lost when a zero is written. prdctl 31 dmaen 30 rsvd 29 rsvd 28 rsvd 27 dir 26 rsvd 25 rsvd 24 start/stop
section 4 register descriptions INIC-1622 data sheet confidential 37 base4/5 + 0ch (ch 0 ) physical region descriptor (prd) table pointer base4/5 + 4ch (ch 1 ) (prdtp) reset: hw reset this register reflects the current physical address of the system memory. in the scatter/gather mode, when bit 7 of the dma command register is set, this register contains the current physical pointer to the scatter/gather list. the descriptor table should be aligned on a dword boundary and cannot cross a 65,536 boundary in memory. bit(s) rw reset acronym definition 31-02 rw 0 (prdtp[31:02]) prd table address : base address of physical descriptor table. 01-00 r 0 (prdtp[01:00]) reserved: always reads 0. physical region descriptor table entry the memory region specified by the descriptor should not straddle a 65,536 boundary. the byte count is 16 bits long and a value of zero indicates 65,536. bit 7 of the last byte indicates the end of table. the bus master operation should be terminated when this bit is set. the sum of the descriptor byte count must be equal to or greater than the size of the disk transfer request. dprdtp 31 prdtp31 23 prdtp23 15 prdtp15 07 prdtp07 30 prdtp30 22 prdtp22 14 prdtp14 06 prdtp06 29 prdtp29 21 prdtp21 13 prdtp13 05 prdtp05 28 prdtp28 20 prdtp20 12 prdtp12 04 prdtp04 27 prdtp27 19 prdtp19 11 prdtp11 03 prdtp03 26 prdtp26 18 prdtp18 10 prdtp10 02 prdtp02 25 prdtp25 17 prdtp17 09 prdtp09 01 prdtp01 = 0 24 prdtp24 16 prdtp16 08 prdtp08 00 prdtp00 = 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 memory region physical base address [31:01] 0 e reserved byte count [15:01] 0
38 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 10h (ch 0 ) physical region descriptor (prd) total transfer base4/5 + 50h (ch 1 ) length (pxfrcnt) reset: hw reset this register reflects the total transfer length of the entire prd chain. bit(s) rw reset acronym definition 31-24 rw 0 (pxfrcnts[07:00]) prd remain count sign bits: these sign bits will be updated after every prd chain completion. 23-00 rw 0 (pxfrcnt[23:00]) prd total transfer count: this counter will be updated after every prd chain completion base4/5 + 14h (ch 0 ) idma control (idmctl) base4/5 + 54h (ch 1 ) reset: hw reset bit(s) rw reset acronym definition 15 rw 0 (mmstr) mirror master: if set to 1 indicates the current sata channel will act as the mirroring master. 14:13 rw 01b (mslvsel[01:00]) slave index: if the current channel is selected to be the master, this 2 bits register selects which channel will act as the mirror slave. 00 = channel 0; 01 = channel 1; 10 = reserved; 11 = reserved note: setting a channel to be both mirror master and slave is prohibited. 12 rw 0 (mslv) mirror slave: if set to 1 indicates the current sata channel will act as a mirroring slave. pxfrcnt 31 pxfrcnts07 23 pxfrcnt23 15 pxfrcnt15 07 pxfrcnt07 30 pxfrcnts06 22 pxfrcnt22 14 pxfrcnt14 06 pxfrcnt06 29 pxfrcnts05 21 pxfrcnt21 13 pxfrcnt13 05 pxfrcnt05 28 pxfrcnts04 20 pxfrcnt20 12 pxfrcnt12 04 pxfrcnt04 27 pxfrcnts03 19 pxfrcnt19 11 pxfrcnt11 03 pxfrcnt03 26 pxfrcnts02 18 pxfrcnt18 10 pxfrcnt10 02 pxfrcnt02 25 pxfrcnts01 17 pxfrcnt17 09 pxfrcnt09 01 pxfrcnt01 24 pxfrcnts00 16 pxfrcnt16 08 pxfrcnt08 00 pxfrcnt00 idmctl 15 mmstr 07 ago 14 mslvsel1 06 apse 13 mslvsel0 05 arstadm 12 mslv 04 aabt 11 rsvd 03 aauten 10 rsvd 02 arsta 09 hwfrzen 01 unfrez 08 aien 00 frezen
section 4 register descriptions INIC-1622 data sheet confidential 39 11-10 r 0 reserved reserved: always reads 0. 09 rw 0 (hwfrzen) hardware freeze enable: if set to 1, it will enable hardware to automatically freeze idma engine if an error status occurs. if cleared, software has full control of when to freeze the idma engine. this bit is used in conjunction with frezen (bit 00 of this register). 08 rw 0 (aien) pci channel interrupt disable: when clear, in the ata regis- ter mode the interrupts generated by the channel are propagated through to the pci bus. when set, interrupts are not propagated to the pci bus. 07 rw 0 (ago) adma go: when set, the adma start to run. when clear, the channel operates only in ata register mode. 06 rw 0 (apse) adma pause: when set, the amda does not follow the cpb chain nor access the cpb lookup table. the software shall pause operations before modifying the cpb chain pointers by the use of apse and apad 05 rw 0 (arstadm) reset adma: set by the host to indicate a reset. cleared by the host after 1us to allow the adma to come out of the idle state. this reset signal will reset the idma engine and abort all pci master con- troller activities. 04 rw 0 (aabt) abort pending commands: a self clearing bit that is set by host software to abort all pending commands. 03 rw 0 (aauten) adma auto-poll enable: this bit is used to enable a device to assert a service interrupt in an overlapped/queued situation. 02 rw 0 (arsta) ata hard reset: when set, the ata reset signal is asserted. if the host set this bit to one, wait for a minimum reset time, and then clear this bit to zero. this reset signal will reset all ata shadow registers and the phy layer. 01 rw 0 (unfrez) unfreeze idma: a self clearing bit that will unfreeze the idma oper- ation after an error condition. 00 rw 0 (frezen) freeze enable: this bit works in conjunction with hwfrzen (bit09 of this register) as shown below: hwfrzen frezen 0 0 idma normal operations 0 1 idma engine is frozen by software until frezen is cleared. 1 0 idma normal operations 1 1 if device returns an error status, idma will be frozen until software writes a 1 to the unfrez bit to unfreeze the idma engine.
40 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 16h (ch 0 ) idma status (idmstat) base4/5 + 56h (ch 1 ) reset: hw reset & channel reset bit(s) rw reset acronym definition 31-24 r 0 reserved reserved: always reads 0. 23 r 0 (adone) adma done: in prd mode, when set, it indicates that the prd has completed. in idma mode, it indicates the amda has finished one or more cpbs. 22 r 1 (apsd) adma pause: when set, indicates the adma has stopped as a result of apse being set and the current transfer has been completed. 21 r 1 (astpd) adma stopped: when set, indicates the amda has stopped as a result of ago being cleared, an error occurring, or no more valid cpbs to be processed. 20 r x (auirq) ata unsolicited irq: when set, indicates the ata unsolicited interrupt line is active. 19 r 1 (algcy) adma legacy: when set, indicates that the adma is in ata register mode. 18 r 0 reserved reserved: always reads 0. 17 r 0 (acpberr) adma cpb error: when set, indicates that at least one of the cpb- error response flags in he cpb has been set to one exception the case of cpsexc and pigex set to one. 16 r 0 (aperr) pci error mode: when set, indicates a pci error has occurred. idmstat 31 rsvd 23 adone 30 rsvd 22 apsd 29 rsvd 21 astpd 28 rsvd 20 auirq 27 rsvd 19 algcy 26 rsvd 18 rsvd 25 rsvd 17 acpberr 24 rsvd 16 aperr
section 4 register descriptions INIC-1622 data sheet confidential 41 base4/5 + 18h (ch 0 ) cpb lookup table address (cpblar) base4/5 + 58h (ch 1 ) reset: hw reset & channel reset the cpb lookup table address is only used in overlapped or queued operation. it is initialized by the system soft- ware with the physical address of the cpb lookup table. bit(s) rw reset acronym definition 31-00 rw 0 (cpblar[31:00]) id ma lookup table address: id ma lookup table register address. base4/5 + 1ch (ch 0 ) posting queue fifo (ptqfifo) base4/5 + 5ch (ch 1 ) reset: hw reset & channel reset this register is used to post command tag?s by the host to the INIC-1622. it is written by the host and read by the dma engine. hardware must insure that the host has access to this register for writes without having to stop the dma engine. this fifo queue can hold up to 32 command tag?s. the posting fifo can be read by the host if nec- essary. bit(s) rw reset acronym definition 07-05 r 0 reserved reserved: always reads 0. 04:00 rw * (ptqfifo[04:00]) posting queue fifo: this is a window into a 32-byte fifo. note: reading this register when the fifo is empty returns ffh. cpblar 31 cpblar31 23 cpblar23 15 cpblar15 07 cpblar07 30 cpblar30 22 cpblar22 14 cpblar14 06 cpblar06 29 cpblar29 21 cpblar21 13 cpblar13 05 cpblar05 28 cpblar28 20 cpblar20 12 cpblar12 04 cpblar04 27 cpblar27 19 cpblar19 11 cpblar11 03 cpblar03 26 cpblar26 18 cpblar18 10 cpblar10 02 cpblar02 25 cpblar25 17 cpblar17 09 cpblar09 01 cpblar01 24 cpblar24 16 cpblar16 08 cpblar08 00 cpblar00 ptqfifo 07 rsvd 06 rsvd 05 rsvd 04 ptqfifo04 03 ptqfifo03 02 ptqfifo02 01 ptqfifo01 00 ptqfifo00
42 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 1dh (ch 0 ) posting queue fifo count (ptqcnt) base4/5 + 5dh (ch 1 ) reset: hw reset & channel reset this read-only register keeps a count of the number of command tag?s in the posting queue fifo. bit(s) rw reset acronym definition 15-14 r 0 reserved reserved: always reads 0. 13-08 r 0 (ptqcnt[05:00]) posting queue fifo count: keeps track of the number of com- mand tag entries in the posting queue fifo. base4/5 + 1eh (ch 0 ) reply queue fifo (rpqfifo) base4/5 + 5eh (ch 1 ) reset: hw reset & channel reset this register is used to reply command tag?s by the INIC-1622 to the host. it is written by the dma engine and read by the host. hardware must insure that the host has access to this register for reads without having to stop the dma engine. this fifo queue can hold up to 32 command tag?s. this fifo is read-only by the host. bit(s) rw reset acronym definition 23-21 r 0 reserved reserved: always reads 0. 20-16 r 0 (rpqfifo[04:00]) reply queue fifo: this is a window into a 32 bytes fifo. note: reading this register when the fifo is empty returns ffh. ptqcnt 15 rsvd 14 rsvd 13 ptqcnt05 12 ptqcnt04 11 ptqcnt03 10 ptqcnt02 09 ptqcnt01 08 ptqcnt00 rpqfifo 23 rsvd 22 rsvd 21 rsvd 20 rpqfifo04 19 rpqfifo03 18 rpqfifo02 17 rpqfifo01 16 rpqfifo00
section 4 register descriptions INIC-1622 data sheet confidential 43 base4/5 + 1fh (ch 0 ) reply queue fifo count (rpqcnt) base4/5 + 5fh (ch 1 ) reset: hw reset & channel reset this read-only register keeps a count of the number of command tag?s in the reply queue fifo. bit(s) rw reset acronym definition 31-30 r 0 reserved reserved: always reads 0. 29-24 r 0 (rpqcnt[05:00]) reply q ueue fifo count: keeps track of the number of completed command tag entries in the reply q ueue fifo. rpqcnt 31 rsvd 30 rsvd 29 rpqcnt05 28 rpqcnt04 27 rpqcnt03 26 rpqcnt02 25 rpqcnt01 24 rpqcnt00
44 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 20h (ch 0 ) serial ata interface status (sstatus) base4/5 + 60h (ch 1 ) reset: hw reset & channel reset this is a read only register which conveys the current state of the interface and host adapter. the content of the regis- ter is updated continuously and asynchronously by the host adapter. bit(s) rw reset acronym definition 31-12 r 0 reserved reserved: always reads 0. 11-08 r 0 (ipm[03:00]) interface power management state: 0000b = device not present or communication not established. 0001b = interface in active state. 0010b = interface in partial power management state. 0110b = interface in slumber power management state. all other values reserved. 07-04 r 0 (spd[03:00]) negotiated interface communication speed: 0000b = no negotiated speed (device not present or communication not established. 0001b = generation 1 communication rate negotiated. all other values reserved. 03-00 r 0 (det[03:00]) interface device detection and phy state: 0000b = no device detected and phy communication not established. 0001b = device presence detected but phy communication not established. 0011b = device presence detected but phy communication established. 0100b = phy in offline mode as a result of the interface being disabled or running in a bist loopback mode all other values reserved. note: the interface must be in the active state for the det value to be accurate. when the interface is in the partial or slumber state, no communication between the host and target is established resulting in a det value corresponding to no device present or no communication established. as a result, the insertion or removal of a device may not be accurately detected under all conditions. sstatus 31 rsvd 23 rsvd 15 rsvd 07 spd03 30 rsvd 22 rsvd 14 rsvd 06 spd02 29 rsvd 21 rsvd 13 rsvd 05 spd01 28 rsvd 20 rsvd 12 rsvd 04 spd00 27 rsvd 19 rsvd 11 ipm03 03 det03 26 rsvd 18 rsvd 10 ipm02 02 det02 25 rsvd 17 rsvd 09 ipm01 01 det01 24 rsvd 16 rsvd 08 ipm00 00 det00
section 4 register descriptions INIC-1622 data sheet confidential 45 base4/5 + 24h (ch 0 ) serial ata error (serror) base4/5 + 64h (ch 1 ) reset: hw reset & channel reset this register conveys the supplemental interface error information to complement the error information available in the shadow register block error register. bit(s) rw reset acronym definition 31-26 r 00h reserved reserved: always reads 0. 25 rw 0 (diagf) unrecognised fis type: when set to 1, this bit indictates that since the bit was last cleared, one or more fis?s were received by the transport layer with good crc but had a fis type field that was not recognized. 24 rw 0 (diagt) transport state transition error: when set to 1, it indi- cates that an error has occurred in the transition from one state to another within the transport layer since the last time this bit was cleared. 23 rw 0 (diags) link sequencer error 22 rw 0 (diagh) handeshake error 21 rw 0 (diagc) crc error 20 rw 0 (diagd) disparity error 19 rw 0 (diagb) 10b to 8b decode error 18 rw 0 (diagw) comm wake 17 rw 0 (diagi) phy internal error 16 rw 0 (diagn) phyrdy change 15-12 r 0h reserved reserved: always reads 0. 11 rw 0 (erre) internal error 10 rw 0 (errp) protocol error 09 rw 0 (errc) non-recovered persistent communication or data integrity error 08 rw 0 (errt) non-recovered transient data integrity error 07-02 r 00h reserved reserved: always reads 0. 01 rw 0 (errm) recovered communication error 00 rw 0 (erri) recovered data integrity error serror 31 rsvd 23 diags 15 rsvd 07 rsvd 30 rsvd 22 diagh 14 rsvd 06 rsvd 29 rsvd 21 diagc 13 rsvd 05 rsvd 28 rsvd 20 diagd 12 rsvd 04 rsvd 27 rsvd 19 diagb 11 erre 03 rsvd 26 rsvd 18 diagw 10 errp 02 rsvd 25 diagf 17 diagi 09 errc 01 errm 24 diagt 16 diagn 08 errt 00 erri
46 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 28h (ch 0 ) serial ata control (scontrol) base4/5 + 68h (ch 1 ) reset: hw reset this register is the interface by which software controls the sata interface capabilities. bit(s) rw reset acronym definition 31-12 r 0 reserved reserved: always reads 0. 11:08 rw 0 (ipm[03:00]) enabled interface power management state: this can be invoked via sata interface power management capabilities. 0000b = no interface power management state restrictions. 0001b = transition to partial power management state disabled. 0010b = transition to slumber power management state disabled. 0110b = transition to both partial and slumber power manage- ment state disabled. all other values reserved. 07:04 rw 0 (spd[03:00]) highest allowed communication speed: 0000b = no speed negotiation restrictions. 0001b = limit speed negotiation to a rate not greater than generation 1 communication rate. all other values reserved. 03:00 rw 0 (det[03:00]) device detection and interface initialization control: 0000b = no device detection or initialization action requested. 0001b = perform interface initialization communication initialization sequence to establish communication. 0100b = disable the sata interface and put phy in offline mode. all other values reserved. svontrol 31 rsvd 23 rsvd 15 rsvd 07 spd03 30 rsvd 22 rsvd 14 rsvd 06 spd02 29 rsvd 21 rsvd 13 rsvd 05 spd01 28 rsvd 20 rsvd 12 rsvd 04 spd00 27 rsvd 19 rsvd 11 ipm03 03 det03 26 rsvd 18 rsvd 10 ipm02 02 det02 25 rsvd 17 rsvd 09 ipm01 01 det01 24 rsvd 16 rsvd 08 ipm00 00 det00
section 4 register descriptions INIC-1622 data sheet confidential 47 base4/5 + 2ch (ch 0 ) serial ata active (sactive) base4/5 + 6ch (ch 1 ) reset: hw reset & channel reset this register shows the status of the sata interface. bit(s) rw reset acronym definition 31-00 rw 0 (sactive[31:00]) serial ata active: bit positions are set to one for each command tag still outstanding. device clears bit positions when command is com- pleted. base4/5 + 3ch external eeprom address (epad) reset: hw reset this register provides the address for the external bios. it also provides auto address increment control. bit(s) rw reset acronym definition 23-19 r 00h reserved reserved: always reads 0. 18:00 rw 0 (epad[18:00]) e 2 prom address: these bits are used to provide the address offset for the device?s bios. sactive 31 sactive31 23 sactive23 15 sactive15 07 sactive07 30 sactive30 22 sactive22 14 sactive14 06 sactive06 29 sactive29 21 sactive21 13 sactive13 05 sactive05 28 sactive28 20 sactive20 12 sactive12 04 sactive04 27 sactive27 19 sactive19 11 sactive11 03 sactive03 26 sactive26 18 sactive18 10 sactive10 02 sactive02 25 sactive25 17 sactive17 09 sactive09 01 sactive01 24 sactive24 16 sactive16 08 sactive08 00 sactive00 epad 23 rsvd 15 epad15 07 epad07 22 rsvd 14 epad14 06 epad06 21 rsvd 13 epad13 05 epad05 20 rsvd 12 epad12 04 epad04 19 rsvd 11 epad11 03 epad03 18 epad18 10 epad10 02 epad02 17 epad17 09 epad09 01 epad01 16 epad16 08 epad08 00 epad00
48 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 3fh external eeprom data port (epdata) reset: hw reset this register provides a data port to read/write data from/to the external bios. bit(s) rw reset acronym definition 31:24 rw * (epdata[07:00]) e 2 prom data port: these bits provide a port to read/write data from/ to the e 2 prom bios. base4/5 + 7ch global control (gctrl) reset: hw reset this register controls various functions of the INIC-1622. bit(s) rw reset acronym definition 15 rw 0 (rpgsel) register page select: 0 = register page 0 will be accessible; 1 = register page 1 will be accessible 14 rw 0 (sint) software interrupt set: this is a self clearing bit that enables the software interrupt, softint, in the gint register. 13 rw 0 (softrst) software reset: a self clearing bit that generates a warm reset to the entire chip. the duration of the software reset equals 3 pci clock wide. this reset signal will reset the entire chip except the pci configuration registers and phy layer. 12 rw 0 (pwrdwn) powerdown: when set, the link-phy interface will go into power- down mode. when clear, link-phy interface will resume operation in normal mode. epdata 31 epdata07 30 epdata06 29 epdata05 28 epdata04 27 epdata03 26 epdata02 25 epdata01 24 epdata00 gctrl 15 rpgsel 07 rsvd 14 sint 06 rsvd 13 softrst 05 led1 12 pwrdwn 04 led0 11 fthd1 03 swled 10 fthd0 02 miren 09 rsvd = 0 01 eeprg 08 gintdis 00 mrmul
section 4 register descriptions INIC-1622 data sheet confidential 49 11:10 rw 00b (ftdh[1:0]) fifo threshold these two bits determine the point at which a pci burst transfer occurs. the definitions are as follows : = 00 - fifo ? full during a read fifo ? empty during write = 01 - fifo full during a read fifo empty during a write = 10 - fifo ? full during a read fifo ? empty during a write = 11 - reserved 09 r 0 reserved reserved: these bits are reserved for future definition. always reads 0. 08 rw 0 (gintdis) global interrupt disable: when set to 1, pci interrupt will be disabled. when set to 0, pci interrupt is enabled. 07-06 r 0 reserved reserved: these bits are reserved for future definition. always reads 0. 05 rw 0 (led1) led1 control: when hwled is set, this port allows software to con- trol the led flash frequency. 04 rw 0 (led0) led0 control: when hwled is set, this port allows software to con- trol the led flash frequency. 03 rw 0 (swled) software control led enable: when set, software has full con- trol of led activity. when clear, the led?s are controlled by hardware. 02 rw 0 (miren) mirroring enable: when set to 1, write data will be mirrored to both channel 0 & channel 1. 01 rw 0 (eeprg) enable eeprom programming: when set, the external eeprom can be programmed. when reset, the external eeprom cannot be pro- grammed. this bit being set also allows the subclass, subsystem device id and subsystem vendor id registers to be programmed. 00 rw 0 (mrmul) enable memory read multiple command: when set, the device as a bus master will use this command to fetch multiple cache lines. when reset, the device will use the memory read command instead. base4/5 + 7eh global status (gstat) reset: hw reset & channel reset this register indicates the type of ata connector being used. bit(s) rw reset acronym definition 31-30 r 0 reserved reserved: always reads 0. gstat 31 rsvd 23 rsvd 30 rsvd 22 rsvd 29 ch1idle 21 rsvd 28 ch0idle 20 rsvd 27 rsvd 19 rsvd 26 rsvd 18 rsvd 25 satapst1 17 rsvd 24 satapst0 16 lddflt
50 confidential INIC-1622 data sheet register descriptions section 4 29 r 1 (ch1idle) channel 1 idle: when set, this bit indicates that channel 1 is idle and there is no pending command 28 r 1 (ch0idle) channel 0 idle: when set, this bit indicates that channel 0 is idle and there is no pending command 27-26 r 0 0 b r eserved reserved: always reads 0. 25 r 0 (satapst1) secondary device present: 1 = device present 0 = no device plugged in 24 r 0 (satapst0) primary device present: 1 = device present 0 = no device plugged in 23-17 r 0 0h reserved reserved: always reads 0. 16 r * ( lddflt) load default status: this bit is set with the value sensed on pin md 2 after a power on reset. md 2 needs to be pulled down if the hardware is to retain the default power on reset values for the following registers: sub system id, sub system vendor id, sub class, vendor id and device id. if the sensed value of pin md 2 after a power on reset is a one (default), then the hardware will load the 72 bit shifted in value from the non vola- tile serial eeprom. the format for this data in the non volatile seeprom is as follows: bytes 0-1 sub system vendor id bytes 2-3 sub system id byte 4 sub class bytes 5-6 vendor id bytes 7-8 device id base4/5 + bch global interrupt status (gints) reset: hw reset & channel reset this register provides the global status of the interrupt inside the INIC-1622. bit(s) rw reset acronym definition 15 r 0 (gint) global interrupt: gints 15 gint 07 rsvd 14 softint 06 rsvd 13 rsvd 05 rsvd 12 rsvd 04 rsvd 11 rsvd 03 rsvd 10 rsvd 02 rsvd 09 rsvd 01 ch1int 08 rsvd 00 ch0int
section 4 register descriptions INIC-1622 data sheet confidential 51 14 r 0 (softint) software interrupt: this bit will be set while software writes ?1? to sint in gctrl register. when software writes ?1?, this bit will be cleared. 13- 0 2 r 0 0h reserved reserved: always reads 0. 01 r 0 (ch1int) channel 1 interrupt: this bit reflects channel 1 interrupt sta- tus[7]. (offset 49[7]) is the masked interrupt status of sata channel 1. 00 r 0 (ch0int) channel 0 interrupt: this bit reflects channel 0 interrupt sta- tus[7]. (offset 09[7]) is the masked interrupt status of sata channel 0. base4/5 + beh global interrupt mask (gimsk) reset: hw reset this register provides the global interrupt mask for various interrupt sources. bit(s) rw reset acronym definition 31 r 0 reserved reserved: always reads 0. 30 r/w 1 (msoftint) mask software interrupt 29-18 r 0h reserved reserved: always reads 0. 17 r/w 1 (mch1int) mask channel 1 interrupt 16 r/w 0 (mch0int) mask channel 0 interrupt gimsk 31 rsvd 23 rsvd 30 msoftint 21 rsvd 29 rsvd 20 rsvd 28 rsvd 20 rsvd 27 rsvd 19 rsvd 26 rsvd 18 rsvd 25 rsvd 17 mch1int 24 rsvd 16 mch0int
52 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + feh non volatile ram port (nvram) reset: hw reset this register provides a mechanism to access the non volatile ram data. bit(s) rw reset acronym definition 23:20 r 0 reserved reserved: always reads 0. 19 r/w 1 (nvrck) non volatile ram clock: this bit is toggled by the controlling driver to clock serial data into and out of the non volatile ram. 18 r/w 0 ( nvrdo) non volatile ram write data: this bit is used to write serial data out to the non volatile ram. 17 r/w 1 (nvren) non volatile ram data output enable: when set the nvrdi output driver will be enabled. when cleared, nvrdi will be in input mode. 16 r/w 0 (nvrdi) non volatile ram read data: this bit is used to read serial data in from the non volatile ram. nvram 23 rsvd = 0 21 rsvd = 0 20 rsvd = 0 20 rsvd = 0 19 nvrck 18 nvrdo 17 nvren 16 nvrdi
section 4 register descriptions INIC-1622 data sheet confidential 53 4.3 page 1 i/o & memory mapped register descriptions these registers are accessible through the first page of pci base address space 4 using io cycles or pci base address space 5 by memory cycles. the register page is selected through gctrl (offset 7c) bit 15. when this bit is cleared, page 1 is selected. base4/5 + 00h (ch 0 ) transport layer debug bus (tp_debug) base4/5 + 40h (ch 1 ) reset: hw reset this 32-bit register is used for debugging purposes. it provides a read port for various transport layer signals. bit(s) rw reset acronym definition 31-00 r 00h (tp_db[31:00]) transport layer debug bus base4/5 + 04h (ch 0 ) link layer debug bus (lk_debug) base4/5 + 44h (ch 1 ) reset: hw reset this 32-bit register is used for debugging purposes. it provides a read port for various link layer signals. bit(s) rw reset acronym definition 31-00 r 00h (lk_db[31:00]) link layer debug bus tp_db3 tp_db2 tp_db1 tp_db0 31 tp_db31 23 tp_db23 15 tp_db15 07 tp_db07 30 tp_db30 22 tp_db22 14 tp_db14 06 tp_db06 29 tp_db29 21 tp_db21 13 tp_db13 05 tp_db05 28 tp_db28 20 tp_db20 12 tp_db12 04 tp_db04 27 tp_db27 19 tp_db19 11 tp_db11 03 tp_db03 26 tp_db26 18 tp_db18 10 tp_db10 02 tp_db02 25 tp_db25 17 tp_db17 09 tp_db09 01 tp_db01 24 tp_db24 16 tp_db16 08 tp_db08 00 tp_db00 lk_db3 lk_db2 lk_db1 lk_db0 31 lk_db31 23 lk_db23 15 lk_db15 07 lk_db07 30 lk_db30 22 lk_db22 14 lk_db14 06 lk_db06 29 lk_db29 21 lk_db21 13 lk_db13 05 lk_db05 28 lk_db28 20 lk_db20 12 lk_db12 04 lk_db04 27 lk_db27 19 lk_db19 11 lk_db11 03 lk_db03 26 lk_db26 18 lk_db18 10 lk_db10 02 lk_db02 25 lk_db25 17 lk_db17 09 lk_db09 01 lk_db01 24 lk_db24 16 lk_db16 08 lk_db08 00 lk_db00
54 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 08h (ch 0 ) current pci bus master address (dcxa) base4/5 + 48h (ch 1 ) reset: hw reset this 32-bit register provides the current pci bus master address. bit(s) rw reset acronym definition 31-00 r 00h (dcxa[31:00]) current pci bus master address base4/5 + 10h (ch 0 ) current pci bus master transfer count (dcxc) base4/5 + 50h (ch 1 ) reset: hw reset this 32-bit register provides the current pci bus master transfer count. bit(s) rw reset acronym definition 31-24 r 00h reserved reserved: always reads 0. 23-00 r 00h (dcxc[23:00]) current pci bus master transfer count dcxa3 dcxa2 dcxa1 dcxa0 31 dcxa31 23 dcxa23 15 dcxa15 07 dcxa07 30 dcxa30 22 dcxa22 14 dcxa14 06 dcxa06 29 dcxa29 21 dcxa21 13 dcxa13 05 dcxa05 28 dcxa28 20 dcxa20 12 dcxa12 04 dcxa04 27 dcxa27 19 dcxa19 11 dcxa11 03 dcxa03 26 dcxa26 18 dcxa18 10 dcxa10 02 dcxa02 25 dcxa25 17 dcxa17 09 dcxa09 01 dcxa01 24 dcxa24 16 dcxa16 08 dcxa08 00 dcxa00 reserved dcxc2 dcxc1 dcxc0 31 rsvd 23 dcxc23 15 dcxc15 07 dcxc07 30 rsvd 22 dcxc22 14 dcxc14 06 dcxc06 29 rsvd 21 dcxc21 13 dcxc13 05 dcxc05 28 rsvd 20 dcxc20 12 dcxc12 04 dcxc04 27 rsvd 19 dcxc19 11 dcxc11 03 dcxc03 26 rsvd 18 dcxc18 10 dcxc10 02 dcxc02 25 rsvd 17 dcxc17 09 dcxc09 01 dcxc01 24 rsvd 16 dcxc16 08 dcxc08 00 dcxc00
section 4 register descriptions INIC-1622 data sheet confidential 55 base4/5 + 14h (ch 0 ) current pci fifo count (fflag) base4/5 + 54h (ch 1 ) reset: hw reset this register provides the current pci data fifo count status. bit(s) rw reset acronym definition 15:09 r 00h reserved reserved: always reads 0. 08-00 r 00h (fflag[08:00]) current pci data fifo count status base4/5 + 18h (ch 0 ) current idma state machine state (idma_sm_cs) base4/5 + 58h (ch 1 ) reset: hw reset this register provides the idma engine state machine current state. bit(s) rw reset acronym definition 15 r 0 r eserved reserved: always reads 0. 1 4- 00 r 00h (idma_sm_cs[1 4: 00]) current idma state machine state fflag1 fflag0 15 rsvd 07 fflag07 14 rsvd 06 fflag06 13 rsvd 05 fflag05 12 rsvd 04 fflag04 11 rsvd 03 fflag03 10 rsvd 02 fflag02 09 rsvd 01 fflag01 08 fflag08 00 fflag00 idma_sm_cs1 idma_sm_cs0 15 rsvd 07 idma_sm_cs07 14 idma_sm_cs 14 06 idma_sm_cs06 13 idma_sm_cs 13 05 idma_sm_cs05 12 idma_sm_cs 12 04 idma_sm_cs04 11 idma_sm_cs 11 03 idma_sm_cs03 10 idma_sm_cs10 02 idma_sm_cs02 09 idma_sm_cs09 01 idma_sm_cs01 08 idma_sm_cs08 00 idma_sm_cs00
56 confidential INIC-1622 data sheet register descriptions section 4 base4/5 + 1ah (ch 0 ) current aprd state machine state (aprd_sm_cs) base4/5 + 5ah (ch 1 ) reset: hw reset this register provides the aprd state machine current state. bit(s) rw reset acronym definition 3 1- 25 r 00h (fpdma_sm_cs[0 7: 0 1] ) current fpdma state machine state 24-16 r 00h (aprd_sm_cs[08:00]) current aprd state machine state base4/5 + 20h (ch 0 ) physical layer debug bus (phy_debug) base4/5 + 60h (ch 1 ) reset: hw reset this 32-bit register is used for debugging purposes. it provides a read port for various phy layer signals. bit(s) rw reset acronym definition 31-00 r 00h (phy_debug[31:00]) physical layer debug bus aprd_sm_cs1 aprd_sm_cs0 31 fpdma_sm_cs0 7 23 aprd_sm_cs07 30 fpdma_sm_cs0 6 22 aprd_sm_cs06 29 fpdma_sm_cs0 5 21 aprd_sm_cs05 28 fpdma_sm_cs0 4 20 aprd_sm_cs04 27 fpdma_sm_cs0 3 19 aprd_sm_cs03 26 fpdma_sm_cs0 2 18 aprd_sm_cs02 25 fpdma_sm_cs0 1 17 aprd_sm_cs01 24 aprd_sm_cs08 16 aprd_sm_cs00 phy_db3 phy_db2 phy_db1 phy_db0 31 phy_db31 23 phy_db23 15 phy_db15 07 phy_db07 30 phy_db30 22 phy_db22 14 phy_db14 06 phy_db06 29 phy_db29 21 phy_db21 13 phy_db13 05 phy_db05 28 phy_db28 20 phy_db20 12 phy_db12 04 phy_db04 27 phy_db27 19 phy_db19 11 phy_db11 03 phy_db03 26 phy_db26 18 phy_db18 10 phy_db10 02 phy_db02 25 phy_db25 17 phy_db17 09 phy_db09 01 phy_db01 24 phy_db24 16 phy_db16 08 phy_db08 00 phy_db00
section 4 register descriptions INIC-1622 data sheet confidential 57 base4/5 + 38h (ch 0 ) physical layer control (phyctl) base4/5 + 78h (ch 1 ) reset: hw reset this 32-bit register is used for debugging purposes. it provides a read/write port for various phy layer control sig- nals. bit(s) rw reset acronym definition 31-00 rw 00h (phyctl[31:00]) physical layer control bus phyctl3 phyctl2 phyctl1 phyctl0 31 phyctl31 23 phyctl23 15 phyctl15 07 phyctl07 30 phyctl30 22 phyctl22 14 phyctl14 06 phyctl06 29 phyctl29 21 phyctl21 13 phyctl13 05 phyctl05 28 phyctl28 20 phyctl20 12 phyctl12 04 phyctl04 27 phyctl27 19 phyctl19 11 phyctl11 03 phyctl03 26 phyctl26 18 phyctl18 10 phyctl10 02 phyctl02 25 phyctl25 17 phyctl17 09 phyctl09 01 phyctl01 24 phyctl24 16 phyctl16 08 phyctl08 00 phyctl00
58 confidential INIC-1622 data sheet register descriptions section 4 4.4 idma sspll i/o register descriptions all the idma sspll i/o registers are accessible through the second page of the pci base address space 4 using i/ o cycles or pci base address space 5 by memory cycles. these registers control the internal spread spectrum pll (sspll) functions. only word writes are valid for the sspll registers. any byte writes will be ignored. writes to address offset 3c-3f will not take effect until a write to address offset bc-bf is being performed. at that moment, all 5 registers will be written as a 64-bit entity. base4/5 + 3ch sspll input divider (sidiv) reset: hw reset bit(s) rw reset acronym definition 15:11 r 0 reserved reserved: always reads 0. 10-09 r/w 10b (inpr[ 01: 0 0] ) programmable input pre-scaler 08-00 r/w 0c0h (ind[08:00]) programmable input divider value base4/5 + 3eh sspll feedback divider (sfdiv) reset: hw reset bit(s) rw reset acronym definition 31 r 0 reserved reserved: always reads 0. 30-29 r/w 10b (fbpr[01:00]) programmable feedback pre-scaler 28-16 r/w 0d80h (fbd[12:00]) programmable feedback divider value sidiv 15 rsvd 07 ind07 14 rsvd 06 ind06 13 rsvd 05 ind05 12 rsvd 04 ind04 11 rsvd 03 ind03 10 inpr 01 02 ind02 09 inpr0 0 01 ind01 08 ind08 00 ind00 sfdiv 31 rsvd 23 fbd07 30 fbpr01 22 fbd06 29 fbpr00 21 fbd05 28 fbd12 20 fbd04 27 fbd11 19 fbd03 26 fbd10 18 fbd02 25 fbd09 17 fbd01 24 fbd08 16 fbd00
section 4 register descriptions INIC-1622 data sheet confidential 59 base4/5 + bch sspll modulation control (smctl) reset: hw reset the power on default is down spread 0.5%. bit(s) rw reset acronym definition 07 r 0 reserved reserved: always reads 0. 06-01 r/w 01h (ssmod[05:00]) ssp control 00 r/w 0 (sson) ssp enable: when set, ssp is enabled. when cleared, ssp is disabled. base4/5 + bdh sspll pll loop (sploop) reset: hw reset bit(s) rw reset acronym definition 23-22 r 00b reserved reserved: always reads 0. 21 r/w 0 (is100) sspll vco current 100 m a enable 20 r/w 0 (lrpi) loop filter resistor control 2 19 r/w 0 (mrpi) loop filter resistor control 1 18 r/w 0 (srpi) loop filter resistor control 0 17 -1 6 r/w 0 1b (vco[01:00]) svco gain control smctl 07 rsvd 06 ssmod05 05 ssmod04 04 ssmod03 03 ssmod02 02 ssmod01 01 ssmod00 00 sson sploop 23 rsvd 22 rsvd 21 is000 20 lrpi 19 mrpi 18 srpi 17 vco01 16 vco00
60 confidential INIC-1622 data sheet register descriptions section 4 4.5 command parameter blocks (cpb) register descriptions the command parameter blocks, which reside in the system memory, is the mechanism through which software uses to issue commands to the host engine. based on the cpb parameters, host hardware will issue the appropriate com- mands to the storage devices. when the command is completed, hardware will update the cpb structure in the system memory with the command status. the cpb structure is described below. 00h response flags (rflag) the response flags describe the status of completed commands. after each command is completed, the response flags will be updated by pci bus master communicating the command status to the host software. bit(s) rw reset acronym definition 07 rw 0 (ccpber) cpb error flag: when set indicates the cpb is inconsistent. 06 rw 0 (cpsexc) aprd excess length error flag: the idma engine will set this bit to 1 if the aprd data transfer length is in excess of that required to complete the command. 05 rw 0 (cpsdef) aprd deficiency length error: the idma engine will set this bit to 1 if the aprd data transfer lengths are insufficient to complete the command. 04 rw 0 (cspnt) ata spurious interrupt error: idma engine dected a spurious interrupt on the ata intrq signal during execution of a command. 03 rw 0 (caterr) ata command error flag: if ata err is set to one during exe- cution of the command, this bit will be set. 02 rw 0 (cignrd) cpb ignored: if the cvld, crel and cdone are all cleared. this bit will be set. 01 rw 0 (crel) ata release flag: if the command is released, this bit will be set. 00 rw 0 (cdone) ata command complete flag: this bit will be set by the idma engine when the command is completed. rflag 07 ccpber 06 cpsexc 05 cpsdef 04 cspnt 03 caterr 02 cignrd 01 crel 00 cdone
section 4 register descriptions INIC-1622 data sheet confidential 61 01h ata error shadow (ataerr ) w hen the host programs the cpb, this byte of data is ignored. at the end of a command, the idma engine will update the content of this register to reflect the content of the ata error register after status update. bit(s) rw reset acronym definition 07:00 rw 0 (ataerr[07:00]) ata error: ata error register content. 02h ata status shadow (atastat ) w hen the host programs the cpb, this byte of data is ignored. at the end of a command, the idma engine will update the content of this register to reflect the content of the ata status register after status update. bit(s) rw reset acronym definition 07:00 rw 0 (atastat[07:00]) ata status: ata status register content. 03h control flags (cflag) the control flags describe the validity and command type of each cpb. bit(s) rw reset acronym definition 07-05 r 0 reserved reserved: always reads 0. ataerr 07 ataerr07 06 ataerr06 05 ataerr05 04 ataerr04 03 ataerr03 02 ataerr02 01 ataerr01 00 ataerr00 ataerr 07 atastat07 06 atastat06 05 atastat05 04 atastat04 03 atastat03 02 atastat02 01 atastat01 00 atastat00 cflag 07 rsvd 06 rsvd 05 rsvd 04 devdir 03 cien 02 rsvd 01 cque 00 cvld
62 confidential INIC-1622 data sheet register descriptions section 4 04 rw 0 (devdir) device direction control: 0 = prd decide direction 1 = device control direction. 03 rw 0 (cien) pci interrupt enable: when set will enable command complete interrupt. 02 r 0 reserved reserved: always reads 0. 01 rw 0 (cque) queued command: this bit should be set for queued commands and cleared otherwise. 00 rw 0 (cvld) cpb valid: it is used in conjuction with cdone and crel to control the processing of the cpb by the idma engine. when cdone is set, the cpb will not be processed. 04h total transfer length ( ctlen) the total transfer length is the number of total bytes to be transfered. bit(s) rw reset acronym definition 31-24 rw 0 (csign[07:00]) sign bits: sign bit duplicated on all 8 bits. 23-00 rw 0 (ctlen[23:00]) transfer length: the total transfer length in bytes of the cpb com- mand. 08h first prd address pointer (cprd) the first prd address pointer points to first prd structure in the system memory. bit(s) rw reset acronym definition 31-00 rw 0 (cprd[31:00]) first prd address pointer: host memory address of the first prd for this cpb. shall be qword aligned. ctlen 31 csign07 23 ctlen23 15 ctlen15 07 ctlen07 30 csign06 22 ctlen22 14 ctlen14 06 ctlen06 29 csign05 21 ctlen21 13 ctlen13 05 ctlen05 28 csign04 20 ctlen20 12 ctlen12 04 ctlen04 27 csign03 19 ctlen19 11 ctlen11 03 ctlen03 26 csign02 18 ctlen18 10 ctlen10 02 ctlen02 25 csign01 17 ctlen17 09 ctlen09 01 ctlen01 24 csign00 16 ctlen16 08 ctlen08 00 ctlen00 cprd 31 cprd31 23 cprd23 15 cprd15 07 cprd07 30 cprd30 22 cprd22 14 cprd14 06 cprd06 29 cprd29 21 cprd21 13 cprd13 05 cprd05 28 cprd28 20 cprd20 12 cprd12 04 cprd04 27 cprd27 19 cprd19 11 cprd11 03 cprd03 26 cprd26 18 cprd18 10 cprd10 02 cprd02 25 cprd25 17 cprd17 09 cprd09 01 cprd01 24 cprd24 16 cprd16 08 cprd08 00 cprd00
section 4 register descriptions INIC-1622 data sheet confidential 63 10h ata shadow register bloc k t he register order is shown in the cpb structure definition table (section 4.5). 13h mirror c ontrol (mirctl) t he mirror control register controls the hardware mirroring functions of the idma engine. bit(s) rw reset acronym definition 31 rw 0 (mmstr) mirror master: if set to 1 indicates the current bus master will act as a mirroring master. 30-29 rw 00b (slvidx) slave index: if the current channel is selected to be the master, this 2- bit register selects which channel will act as the mirror slave. 00 = channel 0 01 = channel 1 10 = reserved 11 = reserved note: setting a channel to be both mirror master and slave is prohibited. 28-2 4 r 0 reserved reserved: always reads 0 . 22h slave ata error shadow (sataerr) w hen the host programs the cpb, this byte of data is ignored. at the end of a mirror write command, the idma engine will update the content of this register to reflect the content of the slave ata error register after status update. bit(s) rw reset acronym definition 07:00 rw 0 (sataerr[07:00]) slave ata error: slave ata error register content. mirctl 31 mmstr 30 slvidx01 29 slvidx00 28 rsvd 27 rsvd 26 rsvd 25 rsvd 24 rsvd sataerr 07 sataerr07 06 sataerr06 05 sataerr05 04 sataerr04 03 sataerr03 02 sataerr02 01 sataerr01 00 sataerr00
64 confidential INIC-1622 data sheet register descriptions section 4 23h slave ata status shadow (satastat ) w hen the host programs the cpb, this byte of data is ignored. at the end of a mirror write command, the idma engine will update the content of this register to reflect the content of the slave ata status register after status update. bit(s) rw reset acronym definition 07:00 rw 0 (satastat[07:00]) slave ata status: slave ata status register content. satastat 07 satastat07 06 satastat06 05 satastat05 04 satastat04 03 satastat03 02 satastat02 01 satastat01 00 satastat00
section 4 register descriptions INIC-1622 data sheet confidential 65 4.6 prd structure register descriptions the physical region descriptors, which reside in the system memory, provide the location and the amount of data to be transferred. the prd structure is described below. 00h physical memory address (pmad) bit(s) rw reset acronym definition 31-00 rw 0 (pmad[31:00]) physical memory address: this is the physical memory address of the start of a physically contiguous memory region. it should be qword aligned. if an i/o transfer, the i/o address of the source or desti- nation of the data. 04h transfer length (plen) bit(s) rw reset acronym definition 15-00 rw 0 (plen[15:00]) transfer length: if ppkt is cleared to zero, plen indicates the length, in qwords, of the transfer segment. if ppkt is set to one and pdint is cleared to zero, plen indicates the length, in words, of the packet command cdb to be transferred. if dint is set to one, plen con- tains a 32-bit message. pmad 31 pmad31 23 pmad23 15 pmad15 07 pmad07 30 pmad30 22 pmad22 14 pmad14 06 pmad06 29 pmad29 21 pmad21 13 pmad13 05 pmad05 28 pmad28 20 pmad20 12 pmad12 04 pmad04 27 pmad27 19 pmad19 11 pmad11 03 pmad03 26 pmad26 18 pmad18 10 pmad10 02 pmad02 25 pmad25 17 pmad17 09 pmad09 01 pmad01 24 pmad24 16 pmad16 08 pmad08 00 pmad00 plen 15 plen15 07 plen07 14 plen14 06 plen06 13 plen13 05 plen05 12 plen12 04 plen04 11 plen11 03 plen03 10 plen10 02 plen02 09 plen09 01 plen01 08 plen08 00 plen00
66 confidential INIC-1622 data sheet register descriptions section 4 07h control flags (pflag) bit(s) rw reset acronym definition 31 rw 0 (pend) aprd chain end: end of aprd chain indicator. 1 = end of chain. 30 rw 0 (piom) io/memory transfer: set to one for i/o transfer, cleared to zero for memory transfer. 29 r 0 reserved reserved: always reads 0. 28 rw 0 (pord) data transfer method: set to one for ulta-dma, cleared to zero for dma assisted pio. 27 rw 0 (pdint) direct interrupt: set to one to indicate that a directed interrupt is to be performed, if a non-error interrupt event occurs. 26 rw 0 (ppkt) packet command pointer: when set, indicates that pmad is a pointer to a packet. plen indicates the length of the packet command cdb to be transferred. pdint shall be cleared to zero when ppkt is set to one. 25 rw 0 (pigex) ignore data excess: when set, indicates to adma that data excess occurring in this aprd is not an error. this is primarily used when reading the results from certain atapi packet commands that return unknown or odd lengths of data. cpsexc will be set but no error interrupt will be generated and the idma continues exexution. 24 r 0 reserved reserved: always reads 0. pflag 31 pend 30 piom 29 rsvd 28 pord 27 pdint 26 ppkt 25 pigex 24 rsvd
INIC-1622 data sheet confidential 67 section 5 electrical specifications 5.1 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.2 recommended operating conditions ta = 0 c to + 115 c v cc_3.3 = 3.3v 5% v cc_1.8 = 1.8 v 5% gnd = 0v table 5-1 absolute maximum ratings parameter minimum maximum units environment storage temperature -40 150 c operating temperature 0 115 c esd immunity 2.0 kv human model voltage levels i/o logic power supply (3.3v) -0.3 3.9 v core logic power supply (1.8v) -0.3 2.0 v inputs -0.3 vcc+0.3 v outputs -0.3 vcc+0.3 v table 5-2 device recommended operating conditions symbol parameter minimum maximum units conditions vcc_3.3 i/o logic supply voltage 3. 14 3.46 v vcc_1.8 core logic supply voltage 1.71 1.89 v v il low level input voltage cmos input ttl input -0.5 -0.5 0.3*v cc 0.8 v guaranteed input low voltage v ih high level input voltage cmos input ttl input 0.7v*v cc 2.0 vdd + 0.5 vdd + 0.5 v guaranteed input high voltage t j junction temperature 0 100 c INIC-1622 data sheet confidential
68 confidential INIC-1622 data sheet electrical specifications section 5 5.3 general dc characteristics ta = 0 c to +115 c v cc_3.3 = 3.3v 5% v cc_1.8 = 1.8v 5% gnd = 0v table 5-3 general dc characteristics symbol parameter minimum typical maximum units i il input leakage current -10 - 10 m a i oz tri-state leakage current -10 - 10 m a c in input capacitance 3.1 pf c out output capacitance 2.7 3.1 4.9 pf c bid bi-directional buffer capacitance 2.7 3.1 4.9 pf
section 5 electrical specifications INIC-1622 data sheet confidential 69 5.4 pci dc parameters ta = 0 c to +75 c v cc = 3.3v 5% v cc_ 1.8 = 1.8v 5% gnd = 0v notes: 1. input currents include hi-z output leakage for all bi-directional buffers with tri-state outputs (ad [31:0], c/be [3:0] #, par, frame#, trdy#, irdy#, devsel#, stop#, perr#, serr#). table 5-4 5v signaling d c parameters symbol parameter conditions minimum maximum units notes v ih input high voltage 2.0 v cc +0.5 v v il input low voltage -0.5 0.8 v i ih input high leakage current v in = 2.7 70 m a 1 i il input low leakage current v in = 0.5 -70 m a 1 v oh output high voltage i out = -2 ma 2.4 v v ol output low voltage i out = 3 ma, 6 ma 0.55 v c in input pin capacitance 10 pf c clk c lk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf table 5-5 3.3v signaling d c parameters symbol parameter conditions minimum maximum units notes v ih input high voltage 0.5v cc v cc + 0.5 v v il input low voltage -0.5 0. 3v cc v v ipu input pull-up voltage 0.7v cc 70 v i il input l eakage current 0 < v in < v cc 10 m a 1 v oh output high voltage i out = - 0.5 m a 0.9v cc v v ol output low voltage i out = 1.5 m a 0.1v cc v c in input pin capacitance 10 pf c clk c lk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf
70 confidential INIC-1622 data sheet electrical specifications section 5 5.5 p ci ac parameters ta = 0 c to +75 c v cc = 3.3v 5% v cc_ 1.8 = 1.8v 5% gnd = 0v notes: 1. refer to the v/i curves. this specification does not apply to clk and rst# which are system outputs. ?switching current high? specifications are not relevant to serr#, and inta# which are open drain outputs . table 5-6 5v signaling a c parameters symbol parameter conditions minimum maximum units notes i oh (ac) switching 0 < v o ut < 1.4 -44 ma 1 current high 1.4 < v o ut < 2.4 -44+(v out -1.4)/0.024 ma 1 3.1< v o ut < v c c eqt?n a 1 (test point) v out = 3.1 -142 ma i ol (ac) switching v out 3 2 .2 95 ma 1 current low 2.2 > v out > 0.55 v out /0.023 ma 1 0.71 > v out > 0 eqt?n b 1 (test point) v out = 0.71 206 ma i cl low clamp current -5 < v in < -1 -25+(v in +1)/0.015 ma slew r output rise slew rate 0.4v to 2.4v load 1 5 v/ns slew r output fall slew rate 2.4v to 0.4v load 1 5 v/ns table 5-7 3.3v signaling a c parameters symbol parameter conditions minimum maximum units notes i oh (ac) switching 0 < v o ut < 0.3v cc - 12v cc ma 1 current high 0.3v cc < v o ut < 0.9v cc -17.1(v cc -vout) ma 1 0.7v cc < v o ut < v c c eqt?n c 1 (test point) v out = 0.7v cc - 32v cc ma i ol (ac) switching v cc > v out 3 0.6v cc 16v cc ma 1 current low 0.6v cc > v out > 0. 1v cc 26.7 v out ma 1 0. 18v cc > v out > 0 eqt?n d 1 (test point) v out = 0. 18v cc -38v cc ma i cl low clamp current - 3 < v in < -1 -25+(v in +1)/0.015 ma i c h high c lamp current v cc +4 > v in 3 v cc +1 2 5+(v in -v cc -1) /0.015 ma slew r output rise slew rate 0.2v cc - 0.6v cc l oad 1 4 v/ns slew f output fall slew rate 0.6v cc - 0.2v cc load 1 4 v/ns
INIC-1622 data sheet confidential 71 section 6 timing specifications 6.1 general timing timing values in the ?preliminary? data sheet are derived from timing simulation. after ac characteriza- tion of the device, the data sheet?s timing values reflect characterization data (unless noted otherwise), at which time ?preliminary? is removed from the data sheet title and footers. 6.1.1 ac input/output timing parameters figure 6-1 ac input/output timing symbol parameter min values typ max units notes tf signal fall time 5 ns cap loading @ 20pf tr signal rise time 5 ns 1.4v 1.4v t 90% 10% 90% 10% tf tr 1.4v 1.4v t ac input conditions ac output timing conditions r 2 c l test point v cc from output under test output test load diagram r 1 confidential
72 confidential INIC-1622 data sheet timing specifications section 6 6.1.2 clock timing parameters 1. rise and fall times are specified in terms of the edge rate measured in v/ns. figure 6-2 clock timing 6.1.3 clock skew timing parameters figure 6-3 clock skew timing 66 mhz 33 mhz symbol parameter min max min max units notes t cyc clock (pclk) period 15 30 30 ns t high clock high pulse width 6 11 ns t low clock low pulse width 6 11 ns - clock slew rate 1.5 4 1 4 v/ns 1 spread spectrum requirements f mod modulation frequency 30 33 khz f spread frequency spread -1 0 % symbol parameter 66 mhz 3.3v signaling 33 mhz 3.3v signaling units notes v test test voltage 0.4 v cc 0.4 v cc v t skew clock skew 1 (max) 2 (max) ns 5 volt clock 2.4 v 0.8 v 1.5 v 2.0 v 0.4 v t low t high t cyc 2.0v , p-to-p (minimum) 3.3 volt clock 0.6 vcc 0.3 vcc 0.4 vcc 0.5 vcc 0.2 vcc 0.4 v cc, p-to-p (minimum) clk v_test t_skew v_test t_skew t_skew v_il v_ih v_ih v_il (@device #1) clk (@device #2)
section 6 timing specifications INIC-1622 data sheet confidential 73 6.2 pci bus timing shown below is the timing diagrams that applies to the 66 mhz and 33 mhz timing parameter table (refer to table 6-1). figure 6-4 output timing measurement conditions figure 6-5 input timing measurement conditions clk output delay tri-state output v_test t_off t_on t_val v_th v_tl v_test (5v signaling) v_trise, v_tfall (3.3v signaling) output current leakage current clk input v_th v_tl v_test v_test v_max v_test v_th v_tl t_su t_h
74 confidential INIC-1622 data sheet timing specifications section 6 notes: 1. preq# and pgnt# are point-to-point signals, and have different input setup times than do bused signals. preq# and pgnt# have a setup of 5ns at 66mhz and 12ns and 10ns respec- tively at 33mhz. all other signals are bused. table 6-1 pci bus 66 mhz and 33 mhz timing parameters 66 mhz 33 mhz symbol parameter min max min max units notes t val clk to signal valid delay - bused signals 2 6 2 11 ns 1 t val (ptp) clk to signal valid delay - point to point signals 2 6 2 12 ns 1 t on float to active delay 2 2 ns t off active to float delay 14 28 ns t su input set up time to clk - bused signals 3 7 ns 1 t su (ptp) input set up time to clk - point to point signals 5 10, 12 ns 1 t h input hold time from clk 0 0 ns t rst reset active time after power stable 1 1 ms t rst-clk reset active time after clk stable 100 100 m s t rst-off reset active to output float delay 40 40 ns t rrsu req64# ti rst# setup time 10t cyc 10t cyc ns t rrh rst# to req64# hold time 50 50 ns t rhfa rst# high to first configuration access 2 25 2 25 clocks t rgff rst# high to first frame# assertion 5 5 clocks
INIC-1622 data sheet confidential 75 section 7 packaging specifications 7.1 INIC-1622 tqfp packaging specifications figure 7-1 shows the physical outline of the 128-pin tqfp package. table 7-1 shows the package?s dimensions. figure 7-1 128 pin tqfp package outline seating plane a d 1 d pin 1 b base metal with plating lead cross-section e 1 e e see detail a all tips a a a c a-b d b b b h a-b d 4x . . . . . . c c c - c - c d d d s m s a-b c d . . . . . . . . . - a - - d - - b - a 1 l a 2 l1 detail a - c - gauge plane 0.25 - h - confidential
76 confidential INIC-1622 data sheet packaging specifications section 7 *notes: 1. dimensions per jedec specification ms-026 issue c. 2. controlling dimensions are in millimeters (mm). 3. the top package body size may be smaller than the bottom package body size by as much as 0.15 mm. 4. datums a-b and -d- to be determined at datum plane -h-. 5. reference plane -h- is located at mold parting line and is coincident with bottom of lead where it exits plastic body. 6. dimensions d and e to be determined at seating plane -c-. 7. dimensions d1 and e1 do not include mold protrusion. allowable protru- sion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 8. dimension b does not include dambar protrusion. allowable dambar pro- trusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm. 9. the dimensions shown in lead cross-section apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 10. dimension a1 is defined as the distance from the seating plane to the low- est point of the package body. 11. solder plate thickness shall be 200 microinches minimum. table 7-1 128-pin tqfp package dimensions mm inch symbol min nom max min nom max a - - 1.20 - - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.13 0.18 0.23 0.005 0.007 0.09 c 0.09 - 0.20 0.004 - 0.008 d 16.00 bsc 0.866 bsc d1 14.00 bsc 0.787 bsc e 16.00 bsc 0.866 bsc e1 14.00 bsc 0.787 bsc e 0.40 bsc 0.016 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref ? 0 deg 3.5 deg 7 deg 0 deg 3.5 deg 7 deg aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
section 7 packaging specifications INIC-1622 data sheet confidential 77
initio corporation 650 north mary ave. sunnyvale, ca 94085-2906 tel: (408) 331-0560 fax: (408) 245-6885 www.initio.com p/n: 1622x-ds rev 1.0 printed in u.s.a 09/03 information is subject to change without notification.

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